Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

In this paper, we propose a novel thin film MOSFET with source/drain tie and discontinuously block oxide layers. Improving process is very important, when the gate length of SOI MOSFET is reduced. To overcome the misalignment problem, we use self-aligned technology to fabricate this device. In addition, the device has discontinuously block oxide layers; they can improve short channel effects, reduce the parasitic capacitance, and decrease the leakage current cause by P-N junction between source/drain and body regions. They also supply two pass ways to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, these two pass ways can be seen as the parallel equivalent resistance results in a reduced series resistance and an increased drain saturation current. According to the ISE TCAD 10.0 simulation results, the discontinuously block oxide layers can not only improve the short channel effects, but also eliminate the floating-body effect and diminish the self-heating effect because of the pass ways.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)).

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)).

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)). / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

A recent evolutionary theory hypothesizes that there are two primary biobehavioral profiles of stress responding. Labeled "hawk" and "dove," each is characterized by divergent patterns of autonomic nervous system and neuroendocrine system activations in response to stress as well as distinct affective and behavioral tendencies. These profiles are prominent in a number of species, and it has been hypothesized that hawk-like and dovelike responses to stress may, in part, explain variability in stress-related health outcomes. This study is a preliminary investigation of hawk and dove biobehavioral profiles in humans. Participants included 73 Midwestern university students recruited from undergraduate-level psychology classes. Upon completion of a stressor task, participants answered questions regarding their psychological experiences during and immediately following the task and reported their emotions and health-related behaviors over the past several weeks. Physiological measures of cortisol and high frequency heart rate variability reactivity were used to identify relatively hawk-like and dove-like responders. Associations between patterns of physiological responding and emotional and behavioral responses were tested. The results showed mixed support for the existence of hawk and dove biobehavioral profiles in humans.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.