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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Working memory constellations

Morris, Neil Gerald January 1986 (has links)
Evidence is presented that supports the view that most models of short-term memory cannot account for the flexibility of the primary memory system. It is argued that the working memory model outlined by Baddeley and Hitch (1974) is, however, a potentially adequate model. Working memory, in this thesis, is depicted as a system that assembles 'constellations' consisting of the central executive and one or more sub-systems. This view suggests a formulation that is considerably more complex than the 1974 model. The empirical studies examine the role of the visuo-spatial scratch pad in the formation and maintenance of working memory constellations. It is concluded from these studies that the scratch pad is independent of the articulatory loop but is usually coupled to the central executive except during maintenance rehearsal. Furthermore, it can be used concurrently with the articulatory loop to process spatial aspects of highly verbal tasks. However a constellation consisting of the executive, the loop and the scratch pad is vulnerable to a wider range of interference effects than a simpler constellation. Paivio (1971) suggested that 'dual coding' leads to better memory performance, however, this is only the case when no distractors are present. The final two chapters present some speculations on how working memory research might proceed in the future. It is concluded that the current trend towards collecting convergent evidence and the emphasis on testing theory in applied situations should give us insights into memory that were not available to Ebbinghaus and other early memory researchers.
2

A radial basis memory model for human maze learning

Drewell, Lisa Y. 30 June 2008 (has links)
This research develops a memory model capable of performing in a human-like fashion on a maze traversal task. The model is based on and retains the underlying ideas of Minerva 2 but is executed with different mathematical operations and with some added parameters and procedures that enable more capabilities. When applied to the same maze traversal task as was used in a previous experiment with human subjects, the performance of a maze traversal agent with the developed model as its memory emulated the error rates of the human data remarkably well. As well, the maze traversal agent and memory model successfully emulated the human data when it was divided into two groups: fast maze learners and slow maze learners. It was able to account for individual differences in performance, specifically, individual differences in the learning rate. Because forgetting was not applied and therefore all experiences were flawlessly encoded in memory, the model additionally demonstrates that error can be due to interference between memories rather than forgetting. / Thesis (Master, Computing) -- Queen's University, 2008-06-04 13:39:38.179
3

Velocity memory

Makin, Alexis David James January 2011 (has links)
It is known that primates are sensitive to the velocity of moving objects. We can also remember velocity information after moving objects disappear. This cognitive faculty has been investigated before, however, the literature on velocity memory to date has been fragmented. For example, velocity memory has been disparately described as a system that controls eye movements and delayed discrimination. Furthermore, velocity memory may have a role in motion extrapolation, i.e. the ability to judge the position of a moving target after it becomes occluded. This thesis provides a unifying account of velocity memory, and uses electroencephalography (EEG) to explore its neural basis. In Chapter 2, the relationship between oculomotor control and motion extrapolation was investigated. Two forms of motion extrapolation task were presented. In the first, participants observed a moving target disappear then reappear further along its path. Reappearance could be at the correct time, too early or too late. Participants discriminated reappearance error with a two-alternative forced choice button press. In the second task, participants saw identical targets travel behind a visible occluder, and they attempted to press a button at the exact time that it reached the other side. Tasks were completed under fixation and free viewing conditions. The accuracy of participant's judgments was reduced by fixation in both tasks. In addition, eye movements were systematically related to behavioural responses, and small eye movements during fixation were affected by occluded motion. These three results imply that common velocity memory and pre-motor systems mediate eye movements and motion extrapolation. In Chapter 3, different types of velocity representation were explored. Another motion extrapolation task was presented, and targets of a particular colour were associated with fast or slow motion. On identical-velocity probe trials, colour still influenced response times. This indicates that long-term colour-velocity associations influence motion extrapolation. In Chapter 4, interference between subsequently encoded velocities was explored. There was robust interference between motion extrapolation and delayed discrimination tasks, suggesting that common processes are involved in both. In Chapter 5, EEG was used to investigate when memory-guided tracking begins during motion extrapolation. This study compared conditions where participants covertly tracked visible and occluded targets. It was found that a specific event related potential (ERP) appeared around 200 ms post occlusion, irrespective of target location or velocity. This component could delineate the onset of memory guided tracking during occlusion. Finally, Chapter 6 presents evidence that a change in alpha band activity is associated with information processing during motion extrapolation tasks. In light of these results, it is concluded that a common velocity memory system is involved a variety of tasks. In the general discussion (Chapter 7), a new account of velocity memory is proposed. It is suggested that a velocity memory reflects persistent synchronization across several velocity sensitive neural populations after stimulus offset. This distributed network is involved in sensory-motor integration, and can remain active without visual input. Theoretical work on eye movements, delayed discrimination and motion extrapolation could benefit from this account of velocity memory.
4

Compiler optimisations and relaxed memory consistency models / Optimisations des compilateurs et modèles mémoire relâchés

Morisset, Robin 05 April 2017 (has links)
Les architectures modernes avec des processeurs multicœurs, ainsi que les langages de programmation modernes, ont des mémoires faiblement consistantes. Leur comportement est formalisé par le modèle mémoire de l'architecture ou du langage de programmation ; il définit précisément quelle valeur peut être lue par chaque lecture dans la mémoire partagée. Ce n'est pas toujours celle écrite par la dernière écriture dans la même variable, à cause d'optimisation dans les processeurs, telle que l'exécution spéculative d'instructions, des effets complexes des caches, et des optimisations dans les compilateurs. Dans cette thèse, nous nous concentrons sur le modèle mémoire C11 qui est défini par l'édition 2011 du standard C. Nos contributions suivent trois axes. Tout d'abord, nous avons regardé la théorie autour du modèle C11, étudiant de façon formelle quelles optimisations il autorise les compilateurs à faire. Nous montrons que de nombreuses optimisations courantes sont permises, mais, surprenamment, d'autres, importantes, sont interdites. Dans un second temps, nous avons développé une méthode à base de tests aléatoires pour détecter quand des compilateurs largement utilisés tels que GCC et Clang réalisent des optimisations invalides dans le modèle mémoire C11. Nous avons trouvés plusieurs bugs dans GCC, qui furent tous rapidement fixés. Nous avons aussi implémenté une nouvelle passez d'optimisation dans LLVM, qui recherchent des instructions des instructions spéciales qui limitent les optimisations faites par le processeur - appelées instructions barrières - et élimine celles qui ne sont pas utiles. Finalement, nous avons développé un ordonnanceur en mode utilisateur pour des threads légers communicants via des canaux premier entré-premier sorti à un seul producteur et un seul consommateur. Ce modèle de programmation est connu sous le nom de réseau de Kahn, et nous montrons comment l'implémenter efficacement, via les primitives désynchronisation de C11. Ceci démontre qu'en dépit de ses problèmes, C11 peut être utilisé en pratique. / Modern multiprocessors architectures and programming languages exhibit weakly consistent memories. Their behaviour is formalised by the memory model of the architecture or programming language; it precisely defines which write operation can be returned by each shared memory read. This is not always the latest store to the same variable, because of optimisations in the processors such as speculative execution of instructions, the complex effects of caches, and optimisations in the compilers. In this thesis we focus on the C11 memory model that is defined by the 2011 edition of the C standard. Our contributions are threefold. First, we focused on the theory surrounding the C11 model, formally studying which compiler optimisations it enables. We show that many common compiler optimisations are allowed, but, surprisingly, some important ones are forbidden. Secondly, building on our results, we developed a random testing methodology for detecting when mainstream compilers such as GCC or Clang perform an incorrect optimisation with respect to the memory model. We found several bugs in GCC, all promptly fixed. We also implemented a novel optimisation pass in LLVM, that looks for special instructions that restrict processor optimisations - called fence instructions - and eliminates the redundant ones. Finally, we developed a user-level scheduler for lightweight threads communicating through first-in first-out single-producer single-consumer queues. This programming model is known as Kahn process networks, and we show how to efficiently implement it, using C11 synchronisation primitives. This shows that despite its flaws, C11 can be usable in practice.
5

Quantifying the Benefits of Immersion for Procedural Training

Sowndararajan, Ajith 04 August 2008 (has links)
Training is one of the most important and widely-used applications of immersive Virtual Reality (VR). Research has shown that Immersive Virtual Environments (IVEs) are beneficial for training motor activities and spatial activities, but it is unclear whether immersive VEs are beneficial for purely mental activities, such as memorizing a procedure. In this thesis, we present two experiments to identify benefits of immersion for a procedural training process. The first experiment is a between-subjects experiment comparing two levels of immersion in a procedural training task. For the higher level of immersion, we used a large L-shaped projection display. We used a typical laptop display for the lower level of immersion. We asked participants to memorize two procedures: one simple and the other complex. We found that the higher level of immersion resulted in significantly faster task performance and reduced error for the complex procedure. As result of the first experiment we performed a controlled second experiment. We compared two within-subjects variables namely environment and location under various treatments formed by combination of three between-subject variables namely Software Field Of View (SFOV), Physical FOV, Field Of Regard (FOR). We found that SFOV is the most essential component for learning a procedure efficiently using IVEs. We hypothesize that the higher level of immersion helped users to memorize the complex procedure by providing enhanced spatial cues, leading to the development of an accurate mental map that could be used as a memory aid. / Master of Science
6

Efficient Runtime Support for Reliable and Scalable Parallelism

Zhang, Minjia January 2016 (has links)
No description available.
7

Intelligent Autonomous Data Categorization

Finegan, Edward Graham 01 January 2005 (has links)
The goal of this research was to determine if the results of a simple comparison algorithm (SCA) could be improved by adding a hyperspace analogue to language model of memory (HAL) layer to form NCA. The HAL layer provides contextual data that otherwise would be unavailable for consideration. It was found that NCA did improve the results when compared to SCA alone. However, NCA added complexity problems that limit its practicality. The complexity of this algorithm is On3 where n is equal to the number of unique symbols in the data. While there is a relativity reasonable soft upper bound for the number of unique symbols used in a language, the complexity still limits the uses of the NCA combined algorithm. The conclusion from this research is that NCA can improve results. This research also suggested that the quality of results might increase as more data is processed by NCA.
8

A direct comparison between mathematical operations in mental arithmetic with regard to working memory’s subsystems

Koch, Felix-Sebastian January 2004 (has links)
<p>This study examined the idea that each mathematical operation (addition, subtraction, multiplication and division) is mainly linked to one of the components of working memory as proposed by Baddeley. The phonological loop, visual-spatial sketchpad and central executive have been studied using a dual-task methodology with 7 different secondary tasks. 35 undergraduate and graduate students were timed in their response time for mental calculation and error rates were calculated. Results show clear differences of operations and of number pairs. Interaction between conditions and operations was just approaching significance. Results did not give support to the idea that operations can be linked to a certain working memory component. Several factors, such as language, problem size, lack for detail in the working memory model, difficulty of the secondary tasks, and internal validity problems are discussed with regard to the results and mental arithmetic.</p>
9

An Interconnection Network for a Cache Coherent System on FPGAs

Mirian, Vincent 12 January 2011 (has links)
Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are processors running software and hardware engines used to accelerate specific functions. To make the programming of such a system simpler, it is easiest to think of a shared-memory environment, much like in current multi-core processor systems. This thesis introduces a novel, shared-memory, cache-coherent infrastructure for heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.
10

An Interconnection Network for a Cache Coherent System on FPGAs

Mirian, Vincent 12 January 2011 (has links)
Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are processors running software and hardware engines used to accelerate specific functions. To make the programming of such a system simpler, it is easiest to think of a shared-memory environment, much like in current multi-core processor systems. This thesis introduces a novel, shared-memory, cache-coherent infrastructure for heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.

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