The present study attempted to incorporate several tests that had specific indices for identifying memory malingering into a battery for the assessment of memory malingering. Two measures, a famous faces test and a subjective memory questionnaire were constructed originally by the author. These measures were pilot-tested on a group of demented community geriatric participants (n=10) and control geriatric participants (n = 12). Three indices indicative of memory malingering in Hong Kong List Learning Test (HKLLT) were explored. The indices of the HKLLT, the two new measures and the Test of Memory Malingering were incorporated into a battery for detection of memory malingering. Using an analogue design, the battery was tested on a group of community participants (N = 58) who were randomized into two conditions, simulated malingering (SM) condition (n = 25, one was excluded because of non-compliance to experimental instructions) and true effort (TE) condition (n = 32). Participants in the SM group were given instruction to exaggerate memory complaints after a hypothetical head injury while the TE condition instructed participants to do his/her best. The subjects were tested on 6 measures of the battery and 2 other tests. A manipulation check was also completed. The results indicated significant difference between the two conditions on all the measures. The cut-off scores of the measures attained sensitivity from .4 to .84 and specificity of .9 to 1. Using discriminant analysis, the overall hit rate was 93% and using logistic regression, the overall hit rate was 98%. The measures were then tested on a group of depressed patients (N = 39) who were randomized into SM (n = 19) and TE condition (n = 20). Manipulation check indicated that about 80% of depressed participants of SM group were unable to comply with malingering instruction. Analysis was then done to compare the performance of community SM sample (n = 25) with community TE sample (n = 32) and depressed TE sample (n = 20). Results found significant difference between simulated malingering and control and depressed sample respectively. No significant difference was found between community control and depressed sample. Using the cut-off scores obtained from the normal sample, specificity of depressed sample on 3 measures was lowered. Using discriminant analysis and logistic regression, two-group classification (simulated malingering and non-simulated malingering) reached an overall hit rate of 92% and 94% respectively. Using 4 indictors of the battery achieved sensitivity of 68%, specificity of 100 % in normal control and 100% in depressed sample. The effect of depression, base rate of malingering in affecting the classification, the issue of use of simulation in research design and future research direction was discussed. / Chang Suk Yi Sonia. / "July 2006." / Adviser: Agnes Chan. / Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1919. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 156-179). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Event related potentials (ERP's) carry very important information that relates to the performance of the brain functions of the human being. Further studies have identified that one component, in particular, P 300, is affected by the memory process. Matched filter is used to improved the SNR of signal ERP' s. We use the output of the matched filter to distinguish the difference of the waveforms between normal subjects and memory-impaired subjects. In our study, we found that the peak values of the matched filtering output were different between normal subjects and memoryimpaired subjects. Also, as an application, wavelet transform is introduced to the ERP analysis. Local maximum of wavelet transform was used as a local feature to find the relationship between the sharp variation points and the memory process. A comparison between matched filtering and wavelet transform was made and also the correlation coefficients of the peaks and sharp variation points are calculated to find the relationship between the important moments in a memory process.

Females exhibit superior object location memory (OLM) compared to males, but the reasons for this sex difference remains unknown. This thesis investigates the role of the dentate gyrus (DG) in an OLM task in normal rats (Experiment 1) and after bilateral adrenalectomy (ADX; Experiment 2). ADX is known to reduce volume of the DG and impair spatial learning. There was no sex difference for OLM in Experiment 1 but females exhibited superior OLM in Experiment 2. Experiment 2 found a significantly smaller DG due to ADX but this had no effect on behaviour. The male DG was significantly larger than the female DG in both experiments. Behaviour during the OLM task was not a predictor of DG volume, although a larger than average DG was related to poor OLM memory in females Thus, the DG involvement for OLM appears to differ between the sexes. / ix, 72 leaves : ill. ; 29 cm

The purpose of this investigation was to compare the performances on the Wide Range Assessment of Memory and Learning (WRAML; Sheslow & Adams, 1990) of children with different developmental and neurological disorders. The primary question was whether the WRAML subtests significantly differentiate among children with Developmental Reading Disorders (RD; n = 44), with Attention-Deficit/Hyperactivity Disorder (ADHD; n = 37), with Traumatic Brain Injury (TBI; n = 30), and without developmental or neurological disabilities (n = 103). Archival data from the TBI Project at James Whitcomb Riley Hospital for Children and from the Division of Psychology at Alfred I. duPont Institute was analyzed. The results of a discriminant functions analysis indicated that significant differences among the groups do exist on the WRAML and that the groups were discriminated from one another by three distinct types of tasks (i.e., functions): rote memory, verbal learning, and meaningful memory. Furthermore, based on WRAML performance alone, participants had a 63% chance of being classified into their proper diagnostic group. In addition to supporting the use of multi-dimensional tasks to assess memory, the results of this study have clinical relevance for developing diagnosis-specific recommendations for memory and learning problems. / Department of Educational Psychology

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.

This study provides information regarding the validity and reliability of the Wood Prospective Meory Test (WPMT), a newly developed test consisting of three main subscales intended to measure prospective memory. Subjects were 69 college students (50 female, 19 male, age range 18-24), who were administered several memory tasks including the WPMT.The results of this study suggest that the subscales of the WPMT do not have sufficient internal reliability (.50, .60, and .44), and therefore, would be unlikely to correlate highly with any other measures. The usefulness of the WPMT as a clinical instrument is discussed.

No description available.

The goal of this work is to understand types of defects in semiconductor memories and algorithms for their testing. In the second part the work describes design and implementation of programmable BIST controller with small digital block size requirments.

Memory monitoring, or the ability to accurately assess one’s memory retrieval success, is known to be declined for older adults. The behavioral decline has been well explored, and is specific to tasks of source monitoring; tasks involving item memory monitoring do not show age-related deficits. This study attempts to further characterize the decline by exploring neuroanatomical contributions to the decline, and genetic influences that may explain performance variability in older adults. Older adults were genotyped for the serotonin transporter (5-HTTLPR) gene, and those that are carriers of the low-expressing allele demonstrate the expected age-related decline of source monitoring performance when compared to younger adults. Interestingly, older adults who lack this allele did not display any decline in performance when compared to younger adults. Neuroanatomical correlates of task performance indicate that prefrontal regions in the inferior and lateral cortices support accurate source memory monitoring, likely through their role in the proper selection of memory cues and inhibition of irrelevant information. This relationship suggests that age-related atrophy occurring in these structures could be responsible for the performance deficits on source memory monitoring tasks. There was no direct relationship seen between genotype for the 5-HTTLPR gene and cortical volumes, however diffusion tensor imaging shows that older adults who carry this allele have altered connections between the medial temporal lobe, responsible for memory retrieval, and prefrontal cortex, which monitors the retrieval process. Through stronger connections of critical networks, older adults who lack the 5-HTTLPR short allele may be able to compensate for the age-related atrophy seen in the prefrontal cortex. Functional results further indicate that the older adult non-carriers recruit inferior and lateral frontal regions to a greater extent than the older adult carriers during accurate memory monitoring. These results begin to suggest a neuroprotective mechanism for the 5-HTTLPR genotype, wherein some older adults may be able to postpone the expected decline of memory monitoring by retaining the ability to recruit essential inferior frontal structures through more organized white matter pathways. / text

La miniaturisation technologique augmente la sensibilité des circuits intégrés auxdéfauts et nous observons à chaque nouvelle génération technologique une dégradation rapidedu rendement de fabrication et de la fiabilité. Les mémoires occupent la plus grande partie dela surface des SoCs et contiennent la vaste majorité des transistors. De plus, pour augmenterleur densité elles sont conçues de façon très serrée. Elles concentrent ainsi la plus grandepartie des défauts de fabrication et représentent aussi les parties les plus sensibles face auxperturbations. Elles sont par conséquent les parties des SoCs les plus affectées par ladégradation du rendement de fabrication et de la fiabilité. L’objectif de cette thèse est deproposer des architectures combinant de façon optimale : algorithmes de test, architecturesBIST, et codes correcteurs d’erreurs afin de proposer des solutions efficaces pourl’amélioration du rendement de fabrication et de la fiabilité des mémoires embarquées. / Nanometric scaling increases the sensitivity of integrated circuits to defects andperturbations. Thus, each new generation of manufacturing process is accompanied by a rapiddegradation of manufacturing yield and reliability. Embedded memories occupy the largestpart of the area of SoCs and comprise the vast majority of transistors. In addition, forincreasing the integration density, they are designed very tightly to the design and electricalrules. Hence, embedded memories concentrate the majority of the manufacturing defectsaffecting a SoC, and are also more sensitive to perturbations. Thus, they are the parts of theSoC the most affected by the deterioration of manufacturing yield and reliability. This thesisdevelops repair architectures optimally combining test algorithms, BIST architectures, anderror correcting codes, in order to propose effective solutions for improving themanufacturing yield and reliability of embedded memories affected by high defect densities.