Finally, the PSRR performance of LDO is studied. An energy-efficient embedded ripple feed-forward path is proposed to improve the PSRR of LDO. Comparing with some state-of-the-art techniques for PSRR improvement, the proposed LDO features very simple structure thus low-power consumption. A LDO implemented in 0.18-mum CMOS technology with 0.042-mm2 active area has been designed to verify the idea. With an external 4.7-muF output capacitor, in the maximum load condition (i.e. at 25 mA), the PSRR is -77 dB at 1 MHz, -85 dB at 2.5 MHz and -55 dB at 5 MHz, respectively. The quiescent current is 15 muA only, while the transient voltage overshoot or undershoot is less than 40 mV when load current changes between 1 mA and 25 mA with 40-ns step time. The LDO achieves good line and load regulations of 3 mV/V and 50 muV/mA, respectively. / Remotely- or battery-powered wireless system-on-a-chip (SoC) needs energy-efficient and high-integration power-management solutions due to their energy-aware characteristics. Low-dropout regulator (LDO) is a good solution because of its excellent performances such as low power consumption, fast load-transient response and high power-supply ripple rejection (PSRR). Moreover, it is easy to be fully integrated since no inductor is needed to be the energy-storage element. Recent development of output-capacitorless LDO (OCL-LDO) realizes on-chip, local voltage regulation to enable more effective integrated power management for SoC. In this thesis, OCL-LDOs with low power consumption and fast load-transient response are investigated and presented in this thesis. LDO with output capacitor for high-PSRR operation to provide clean power supply to RF circuits is also reported. Three LDOs are developed and fabricated to verify the proposed ideas. / The first design is an ultra low-power voltage regulator for remotely powered energy-autonomous devices. It has been fabricated in a commercial 0.18-mum CMOS technology and applied to a passive UHF RFID tag IC. With the low-power voltage reference circuit and sub-threshold operations, the total quiescent current is 700 nA under a 1.8-V power supply. The output voltage of the regulator is 1.45 V with load capability of 50 muA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/°C, respectively. A POR signal with 150-ns-width pulse is also generated to reset the digital processing part in the tag IC. / The second design is a fast-transient OCL-LDO, which has been implemented in a commercial 90-nm CMOS technology. Experimental result verifies that it is stable for a capacitive load from 0 to 50 pF and with load capability of 100 rnA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the power transistor promptly. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 mus. While the measured power consumption is only 6 muW under a 0.75-V supply. / Guo, Jianping. / Adviser: Ka Nang Leung. / Source: Dissertation Abstracts International, Volume: 73-06, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Hon Kwok-Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1. --- System Architecture --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Receiver Architectures --- p.2 / Chapter 1.2.1 --- Superheterodyne Receiver --- p.2 / Chapter 1.2.2 --- Homodyne Receiver --- p.3 / Chapter 1.2.3 --- Image-Reject Receiver --- p.5 / Chapter 1.2.4 --- Low intermediate frequency Receiver --- p.7 / Chapter 1.3 --- Double Intermediate Frequency Receivers --- p.8 / Chapter 1.3.1 --- Introduction --- p.8 / Chapter 1.3.2 --- Background Theory --- p.8 / Chapter 2. --- Receiver Fundamentals --- p.23 / Chapter 2.1 --- Noise model --- p.23 / Chapter 2.1.1 --- Thermal noise of resistors --- p.23 / Chapter 2.1.2 --- Channel noise of transistors --- p.24 / Chapter 2.2 --- Noise Figure --- p.26 / Chapter 2.3 --- Linearity --- p.26 / Chapter 2.3.1 --- 1 -dB Compression point --- p.27 / Chapter 2.3.2 --- Third Intercept point (IP3) --- p.28 / Chapter 2.3.3 --- Dynamic Range (DR) --- p.30 / Chapter 2.3.3.1 --- Spurious-Free Dynamic Range (SFDR) --- p.30 / Chapter 2.3.3.2 --- Blocking Dynamic Range (BDR) --- p.32 / Chapter 3. --- Spiral Inductor --- p.33 / Chapter 3.1 --- Spiral inductor modeling --- p.34 / Chapter 3.2 --- Spiral Inductor model parameters --- p.36 / Chapter 3.3 --- Characteristic of spiral inductor --- p.36 / Chapter 3.4 --- Inductor Design and Optimization --- p.37 / Chapter 4. --- Low Noise Amplifier (LNA) --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Common LNA Architectures --- p.39 / Chapter 4.2.1 --- Resistive Termination --- p.39 / Chapter 4.2.2 --- 1/gm Termination --- p.42 / Chapter 4.2.3 --- Shunt-Series Feedback --- p.43 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.43 / Chapter 4.3 --- Full Schematic diagram of the Low Noise Amplifier --- p.45 / Chapter 4.4 --- Full noise analysis of the LNA using inductive source degeneration --- p.46 / Chapter 4.4.1 --- Output noise due to channel noise --- p.46 / Chapter 4.4.1.1 --- Output noise due to i2d --- p.47 / Chapter 4.4.1.2 --- "Output noise due to i2g,u" --- p.47 / Chapter 4.4.1.3 --- "Output noise due to i2g,c and i2d" --- p.49 / Chapter 4.4.2 --- "Output noise due to Rg R,l Rs" --- p.51 / Chapter 4.4.3 --- Noise factor calculation --- p.52 / Chapter 4.4.3.1 --- Rl calculation --- p.52 / Chapter 4.4.3.2 --- Rg calculation --- p.52 / Chapter 4.4.3.3 --- Ql calculation --- p.53 / Chapter 4.4.3.4 --- wT calculation --- p.53 / Chapter 4.4.3.5 --- x calculation --- p.53 / Chapter 4.5 --- Simulation Result of the low noise amplifier (100 finger gate poly) --- p.54 / Chapter 4.5 --- Experimental Result of the low noise amplifier (100 finger gate poly) --- p.56 / Chapter 5. --- Down-conversion Mixer --- p.58 / Chapter 5.1 --- Introduction --- p.58 / Chapter 5.2 --- Gilbert Cell Mixer --- p.59 / Chapter 5.2.1 --- Circuit Description --- p.59 / Chapter 5.2.2 --- Basic Operation --- p.60 / Chapter 5.2.3 --- Simulation Result of the Gilbert Cell Mixer --- p.62 / Chapter 5.3 --- Single-ended to Differential-ended Converter --- p.66 / Chapter 5.3.1 --- Simulation Result of the Single-Ended to Differential-Ended Converter --- p.68 / Chapter 5.4 --- Experimental Result of The Gilbert Cell Mixer --- p.70 / Chapter 5.4.1 --- 1-dB compression point experiment --- p.70 / Chapter 5.4.2 --- IIP3 experimental setup and result --- p.72 / Chapter 5.4.3 --- "Experimental result of 1 -dB compression point, IIP3, conversion gain, SFDR and BDR" --- p.74 / Chapter 5.4.4 --- LO power verse conversion gain --- p.75 / Chapter 5.4.5 --- Intermediate frequency verse conversion gain --- p.77 / Chapter 5.4.6 --- Experimental result of input matching and isolation --- p.78 / Chapter 6. --- Asymmetric Polyphase Network --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Performance of the Asymmetric Polyphase Network --- p.81 / Chapter 6.2.1 --- First Building Block --- p.82 / Chapter 6.2.2 --- Second Building Block --- p.83 / Chapter 6.2.3 --- Third Building Block --- p.84 / Chapter 6.2.4 --- Forth Building Block --- p.84 / Chapter 6.3 --- Simulation result of the asymmetric polyphase network --- p.85 / Chapter 6.4 --- Experimental result of the asymmetric polyphase network --- p.86 / Chapter 7. --- Conclusion --- p.87 / Chapter 8. --- Reference --- p.89 / Chapter 9. --- Appendix A --- p.92 / Chapter 10. --- Appendix B --- p.95 / Chapter 11. --- Appendix C --- p.98 / Chapter 12. --- Appendix D --- p.99

Hiu Yung Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 104-111). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objectives --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Organization of the Thesis --- p.4 / Chapter 2 --- Devices and Fabrication Processes --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- BJTs --- p.6 / Chapter 2.2.1 --- Structure and Modeling of BJTs --- p.6 / Chapter 2.2.2 --- Standard BJT Process and BJT Characteristics --- p.7 / Chapter 2.3 --- MOSFETs and Complementary MOS (CMOS) --- p.8 / Chapter 2.3.1 --- Structure and Modeling of MOSFETs --- p.8 / Chapter 2.3.2 --- Standard n-well CMOS Process and MOSFETs Charac- teristics --- p.11 / Chapter 2.4 --- BiCMOS Technology --- p.13 / Chapter 2.5 --- Summary --- p.14 / Chapter 3 --- Matching Properties --- p.15 / Chapter 3.1 --- Introduction --- p.15 / Chapter 3.2 --- Importance of Matched Devices in IC Design --- p.15 / Chapter 3.2.1 --- What is Matching? --- p.15 / Chapter 3.2.2 --- Low-power Systems --- p.16 / Chapter 3.2.3 --- Device Size Downward Scaling --- p.16 / Chapter 3.2.4 --- Analog Circuits and Analog Computing --- p.17 / Chapter 3.3 --- Measurement of Mismatch --- p.18 / Chapter 3.3.1 --- Definitions and Statistics of Mismatch --- p.18 / Chapter 3.3.2 --- Types of Mismatches --- p.20 / Chapter 3.3.3 --- Matching Properties of MOSFETs --- p.23 / Chapter 3.3.4 --- Matching Properties of BJTs and CLBTs --- p.27 / Chapter 3.4 --- Summary --- p.30 / Chapter 4 --- CMOS Compatible Lateral Bipolar Transistors (CLBTs) --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Structure and Operation --- p.32 / Chapter 4.3 --- DC Model of CLBTs --- p.34 / Chapter 4.4 --- Residual Gate Effect in Accumulation --- p.35 / Chapter 4.5 --- Main Characteristics of CLBTs --- p.37 / Chapter 4.5.1 --- Low Early Voltage --- p.37 / Chapter 4.5.2 --- Low Lateral Current Gain at High Current Levels --- p.38 / Chapter 4.5.3 --- Other Issues --- p.39 / Chapter 4.6 --- Enhanced CLBTs with Cascode Circuit --- p.40 / Chapter 4.7 --- Applications --- p.41 / Chapter 4.8 --- Design and Layout of CLBTs --- p.42 / Chapter 4.9 --- Experimental Results of Single pnp CLBT； nMOSFET and pMOSFET --- p.44 / Chapter 4.9.1 --- CLBT Gains --- p.46 / Chapter 4.9.2 --- Gate Voltage Required for Pure Bipolar Action --- p.47 / Chapter 4.9.3 --- I ´ؤ V and Other Characteristics of Bare pnp CLBTs --- p.49 / Chapter 4.9.4 --- Transfer Characteristics of a Cascoded pnp CLBT --- p.50 / Chapter 4.9.5 --- Transfer Characteristics of an nMOSFET --- p.51 / Chapter 4.9.6 --- Transfer Characteristics of Cascoded and Bare CLBTs Operating as pMOSFETs --- p.52 / Chapter 4.10 --- Summary --- p.53 / Chapter 5 --- Experiments on Matching Properties --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Objectives --- p.55 / Chapter 5.3 --- Technology --- p.57 / Chapter 5.4 --- Design of Testing Arrays --- p.57 / Chapter 5.4.1 --- nMOSFET Array --- p.57 / Chapter 5.4.2 --- pnp CLBT Array --- p.59 / Chapter 5.5 --- Design of Input and Output Pads (I/O Pads) --- p.62 / Chapter 5.6 --- Shift Register --- p.62 / Chapter 5.7 --- Experimental Equipment --- p.63 / Chapter 5.8 --- Experimental Setup for Matching Properties Measurements --- p.65 / Chapter 5.8.1 --- Setup for Measuring the Mismatches of the Devices --- p.65 / Chapter 5.8.2 --- Testing Procedures --- p.68 / Chapter 5.8.3 --- Data Analysis --- p.68 / Chapter 5.9 --- Matching Properties --- p.69 / Chapter 5.9.1 --- Matching Properties of nMOSFETs --- p.69 / Chapter 5.9.2 --- Matching Properties of CLBTs --- p.71 / Chapter 5.9.3 --- Matching Properties of pMOSFETs --- p.73 / Chapter 5.9.4 --- "Comments on the Matching Properties of CLBT, nMOSFET, and pMOSFET" --- p.76 / Chapter 5.9.5 --- "Mismatch in CLBT, nMOSFET, and pMOSFET Cur- rent Mirrors" --- p.77 / Chapter 5.10 --- Summary --- p.79 / Chapter 6 --- Conclusion --- p.80 / Chapter A --- Floating Gate Technology --- p.82 / Chapter A.1 --- Floating Gate --- p.82 / Chapter A.2 --- Tunnelling --- p.83 / Chapter A.3 --- Hot Electron Effect --- p.85 / Chapter A.4 --- Summary --- p.86 / Chapter B --- A Trimmable Transconductance Amplifier --- p.87 / Chapter B.1 --- Introduction --- p.87 / Chapter B.2 --- Trimmable Transconductance Amplifier using Floating Gate Com- patible Lateral Bipolar Transistors (FG-CLBTs) --- p.87 / Chapter B.2.1 --- Residual Gate Effect and Collector Current Modulation --- p.89 / Chapter B.2.2 --- Floating Gate CLBTs --- p.92 / Chapter B.2.3 --- Electron Tunnelling --- p.93 / Chapter B.2.4 --- Hot Electron Injection --- p.94 / Chapter B.2.5 --- Experimental Results of the OTA --- p.94 / Chapter B.2.6 --- Experimental Results of the FGOTA --- p.96 / Chapter B.3 --- Summary --- p.97 / Chapter C --- AMI-ABN 1.5μm n-well Process Parameters (First Batch) --- p.98 / Chapter D --- AMI-ABN 1.5μm n-well Process Parameters (Second Batch) --- p.101 / Bibliography --- p.104

Chan Shek-Hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 94-97). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Table of Contents --- p.v / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Significance of the research --- p.2 / Chapter 1.3 --- Objectives --- p.3 / Chapter 1.4 --- Thesis outline --- p.4 / Chapter Chapter 2 --- Background theory --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Electrical properties of MOS transistors --- p.5 / Chapter 2.2.1 --- Strong inversion --- p.5 / Chapter 2.2.2 --- Weak inversion --- p.6 / Chapter 2.2.3 --- Moderate inversion --- p.8 / Chapter 2.2.4 --- The transistors biased in this work --- p.8 / Chapter 2.3 --- Rail-to-rail signals --- p.8 / Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10 / Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10 / Chapter 2.4.1.1 --- Principle --- p.10 / Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13 / Chapter 2.4.2 --- Folded-cascode gain stage --- p.14 / Chapter 2.5 --- The nature of operational amplifier distortion --- p.16 / Chapter 2.5.1 --- The total harmonic distortion --- p.17 / Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- Review of constant-gm input stage --- p.20 / Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20 / Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21 / Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23 / Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25 / Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28 / Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28 / Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30 / Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31 / Chapter 3.3 --- Conclusion --- p.32 / Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Principle of the conventional input stage --- p.35 / Chapter 4.2.1 --- Translinear circuit --- p.35 / Chapter 4.3 --- Previous work --- p.36 / Chapter 4.3.1 --- Input bias circuit --- p.36 / Chapter 4.3.2 --- Weak inversion operation --- p.38 / Chapter 4.3.3 --- Power up problem --- p.43 / Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47 / Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47 / Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50 / Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51 / Chapter Chapter 5 --- Simulation Results --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- DC bias simulation --- p.54 / Chapter 5.2.1 --- Total transconductance variation --- p.54 / Chapter 5.2.2 --- Power consumption --- p.56 / Chapter 5.3 --- AC simulation --- p.56 / Chapter 5.3.1 --- Open-loop gain --- p.57 / Chapter 5.3.2 --- Gain-bandwidth product --- p.59 / Chapter 5.3.3 --- Phase margin --- p.59 / Chapter 5.4 --- Transient simulation --- p.60 / Chapter 5.4.1 --- Voltage follower --- p.60 / Chapter 5.4.2 --- Total harmonic distortion --- p.62 / Chapter 5.4.3 --- Step response --- p.65 / Chapter 5.5 --- Conclusion --- p.67 / Chapter Chapter 6 --- Layout Consideration --- p.68 / Chapter 6.1 --- Introduction --- p.68 / Chapter 6.2 --- Substrate tap --- p.68 / Chapter 6.3 --- Input protection circuitry --- p.69 / Chapter 6.4 --- Die micrographs of the OTA --- p.71 / Chapter Chapter 7 --- Measurement Results --- p.74 / Chapter 7.1 --- Introduction --- p.74 / Chapter 7.2 --- DC bias measurement results --- p.74 / Chapter 7.2.1 --- Total transconductance variation --- p.74 / Chapter 7.2.2 --- Power consumption --- p.77 / Chapter 7.3 --- AC measurement results --- p.78 / Chapter 7.3.1 --- Open-loop gain --- p.78 / Chapter 7.3.2 --- Gain-bandwidth product --- p.81 / Chapter 7.3.3 --- Phase margin --- p.81 / Chapter 7.4 --- Transient measurement result --- p.82 / Chapter 7.4.1 --- Voltage follower --- p.82 / Chapter 7.4.2 --- Total harmonic distortion --- p.85 / Chapter 7.4.3 --- Step response --- p.87 / Chapter 7.5 --- Conclusion --- p.88 / Chapter Chapter 8 --- Conclusion --- p.90 / Chapter 8.1 --- Contribution --- p.90 / Chapter 8.2 --- Further development --- p.91 / Chapter Chapter 9 --- Appendix --- p.92 / Chapter Chapter 10 --- Bibliography --- p.94

by Fong Hon Hang = 超薄二氧化硅的固定電荷分佈和電擊穿特性 / 方漢鏗. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references. / Text in English; abstracts in English and Chinese. / by Fong Hon Hang = Chao bo er yang hua gui de gu ding dian he fen bu he dian ji chuan te xing / Fang Hankeng. / ABSTRACT --- p.i / ACKNOWLEDGEMENTS --- p.iii / TABLE OF CONTENT --- p.iv / LIST OF FIGURES --- p.ix / LIST OF TABLES --- p.xiv / LIST OF SYMBOLS --- p.xv / Chapter Chapter1 --- Background of the thesis work / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Stability of charge on oxide --- p.1 / Chapter 1.3 --- Defects in SiO2/Si --- p.2 / Chapter 1.4 --- Objectives of the thesis work --- p.4 / Chapter 1.5 --- Organization of the thesis --- p.5 / Bibliography for Chapter1 --- p.6 / Chapter Chapter2 --- Theory of X-ray Photoelectron Spectroscopy (XPS) and Surface Charge Spectroscopy (SCS) / Chapter 2.1 --- Introduction --- p.7 / Chapter 2.2 --- X-ray photoelectron spectrometry (XPS) --- p.8 / Chapter 2.2.1 --- Binding energy reference for semiconductors --- p.10 / Chapter 2.2.2 --- Measurement of surface Fermi level --- p.15 / Chapter 2.2.3 --- XPS quantitative analysis --- p.17 / Chapter 2.2.3.1 --- Electron Inelastic Mean free Path --- p.16 / Chapter 2.2.3.2 --- Atomic concentration of a homogeneous material --- p.17 / Chapter 2.2.3.3 --- Determination of overlayer thickness --- p.19 / Chapter 2.3 --- Surface charge Spectroscopy (SCS) --- p.21 / Chapter 2.3.1 --- Principle of the SCS technique --- p.21 / Chapter 2.3.2 --- Control of the dielectric surface potential --- p.21 / Chapter 2.3.3 --- Dielectric layer surface potential --- p.22 / Chapter 2.3.4 --- Surface band bending --- p.23 / Chapter 2.3.5 --- Limitation of the dielectric layer thickness --- p.24 / Chapter 2.4 --- Applications of SCS on Metal-Oxide Semiconductor (MOS) --- p.24 / Chapter 2.4.1 --- Measurements of interface state density (Dit) --- p.24 / Chapter 2.4.2 --- Determination of density of fixed-oxide charges --- p.27 / Bibliography for Chapter2 --- p.28 / Chapter Chapter3 --- Instrumentation & methodology / Chapter 3.1 --- X-ray Photoelectron Spectroscopy (XPS) --- p.30 / Chapter 3.1.1 --- General description of the Kratos AXIS - HS XPS system --- p.30 / Chapter 3.1.2 --- X-ray source --- p.32 / Chapter 3.1.3 --- AXIS - HS electron analyzer and transfer lens system --- p.35 / Chapter 3.1.4 --- Laser alignment facility --- p.38 / Chapter 3.1.5 --- In-lens (Micro XPS) aperture --- p.38 / Chapter 3.1.6 --- Iris (Lens input aperture) --- p.39 / Chapter 3.1.7 --- Magnetic immersion lenses --- p.39 / Chapter 3.1.8 --- Lateral resolutions --- p.41 / Chapter 3.1.9 --- Charge neutralizer --- p.53 / Chapter 3.1.10 --- XPS imaging capability --- p.58 / Chapter 3.1.11 --- Angle-resolved X-ray photoelectron spectroscopy (ARXPS) --- p.58 / Chapter 3.1.12 --- Ion sputtering system and depth profiling --- p.59 / Chapter 3.2 --- Methodology for surface charging --- p.59 / Chapter 3.3 --- Sample preparation --- p.61 / Bibliography for Chapter3 --- p.62 / Chapter Chapter4 --- Fixed-oxide charge Qf(z) of thermally-grown SiO2/Si(100) / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Experimental results on oxide surface potential as a function of oxide thickness --- p.64 / Chapter 4.3 --- Calculation of fixed-oxide charge distribution --- p.69 / Chapter 4.3.1 --- Gauss's law --- p.69 / Chapter 4.3.2 --- Density of fixed-oxide charge --- p.70 / Chapter 4.4 --- Applications --- p.78 / Bibliography for chapter4 --- p.80 / Chapter Chapter5 --- Observation of dielectric electrical breakdown phenomena of SiO2/Si structure by SCS / Chapter 5.1 --- Introduction to electrical breakdown analysis in device electronics --- p.81 / Chapter 5.2 --- Experimental --- p.82 / Chapter 5.3 --- Results --- p.82 / Chapter 5.3.1 --- Analysis on 1000A Sio2/Si --- p.82 / Chapter 5.3.1.1 --- Variation of C 1s under charging --- p.82 / Chapter 5.3.1.2 --- Stochastic breakdown of SiO2 --- p.84 / Chapter 5.3.2 --- Analysis on 19k SiO2/Si --- p.91 / Chapter 5.4 --- Discussion --- p.93 / Chapter 5.4.1 --- Model of stochastic breakdown of SiO2/Si --- p.93 / Chapter 5.4.2 --- Variation of Si 2p under charging --- p.95 / Chapter 5.5 --- Summary --- p.96 / Bibliography for Chapter5 --- p.99 / Chapter Chapter6 / Conclusion --- p.100

Sun, Lei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Lennox P. John Hoyte. / M.S.

The increased use of DC-consuming electronics in many applications relevant to everyday life, necessitates significant improvements to power conversion and distribution methodologies. The surge in mobile electronics created a new power application space where high efficiency, size, and reduced complexity are critical, and at the same time, many computational tasks are relegated to centralized cloud computing centers, which consume significant amounts of energy. In both those application spaces, conversion and distribution efficiency improvements of even a few-% proves to be more and more challenging. A lot of research and development efforts target each source of loss, in an attempt to improve power electronics such that it serves the advances in other fields of electronics. Non-isolated DC-DC converters are essential in every electronics system, and improvements to efficiency, volume, weight and cost are of utmost interest. In particular, increasing the operation frequency and the conversion ratio of such converters serves the purposes of reducing the number or required conversion steps, reducing converter size, and increasing efficiency. The aforementioned improvements can be achieved by using superior technologies for the components of the converter, and by implementing higher level of integration than most present-day converters exhibit. In this work, Gallium Nitride (GaN) high electron mobility transistors (HEMT) are utilized as switches in a half-bridge buck converter topology, in conjunction with fine-line 180nm complementary metal oxide semiconductor (CMOS) driver circuitry. The circuits are integrated through a face-to-face bonding technique which results in significant reduction in interconnects parasitics and allows faster, more efficient operation. This work shows that the use of GaN transistors for the converter gives an efficiency headroom that allow pairing converters with state-of-the-art thin-film inductors with magnetic material, a task that is currently usually relegated to air-core inductors. In addition, a new "core-clad" structure for thin-film magnetic integrated inductors is presented for the use with fully integrated voltage regulators (IVRs). The core-clad topology combines aspects from the two popular inductor topologies (solenoid and cladded) to achieve higher inductance density and improved high frequency performance.

Wireless communication circuits rely on the use of high-quality passive elements (inductor-capacitor resonant tanks) for the implementation of selective filters and high-purity frequency references (oscillators). Typically available CMOS, on-chip passives suffer from high losses, primarily inductors, and consume large areas that cannot be populated by transistors leading to a significant area penalty. Mechanical resonators exhibit significantly lower losses than their electrical counterparts due to the reduced parasitic loss mechanisms in the mechanical domain. Efficient transduction schemes such as the piezoelectric effect allow for simple electrical actuation and read-out of such mechanical resonators. Piezoelectric thin-film bulk acoustic resonators (FBARs) are currently among the most promising and widely used mechanical resonator structures. However, FBARs are currently only available as off-chip components, which must be connected to CMOS circuitry through wire-bonding and flip-chip schemes. The use of off-chip interfaces introduces considerable parasitics and significant limitations on integration density. Monolithic integration with CMOS substrates alleviates interconnect parasitics, increases integration density and allows for area sharing whereby FBARs reside atop active CMOS circuitry. Close integration of FBARs and CMOS transistors can also enable new circuit paradigms, which simultaneously leverage the strengths of both components. Described here, is a body of work conducted to integrate FBAR resonators with active CMOS substrates (180nm and 65nm processes). A monolithic fabrication method is described which allows for FBAR devices to be constructed atop the backend small CMOS dies through low thermal-budget (< 300°C) post-processing. Stand-alone fabricated devices are characterized and the extracted electrical model is used to design two oscillator chips. The chips comprise amplifier circuitry that functions along with the integrated FBARs to achieve oscillation in the 0.8-2 GHz range. The chips also include test structures to assess the performance of the underlying CMOS transistors before and after the resonator post-processing. A successful FBAR-CMOS oscillator is demonstrated in 65nm CMOS along with characterization of FBARs built on CMOS. The approach presented here can be used for experimenting with more complex circuits leveraging the co-integration of piezoelectric resonators and CMOS transistors.

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam.