Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise.

Software cognitive radios and Internet of Things (IoT) are recent interest areas that need low loss and low power consumption hardware. More specifically, the area of software cognitive radios requires that hardware be frequency agile and highly selective. Meanwhile, IoT relies on multiple low power sensor networks. By combining Complementary Metal Oxide Semiconductors (CMOS) technology with piezoelectric Micro-Electro-Mechanical Systems (MEMS), we can fabricate Systems-on-Chip (SoC) that can be used as filters or references (oscillators) and highly selective sensors. In this work we developed a die-level compatible process for the monolithic integration of Bulk Acoustic Resonators (BAWs) on CMOS for low power, reduced area and high-quality passives for radio frequency applications. Using CMOS as a fabrication substrate some stringent requirements were added to maintain the dies and the technology’s integrity. A few of these limitations were the need for a low thermal budget fabrication process, die handling and electro-static discharge (ESD) protection. The devices were first fabricated on glass for modeling extraction that was later used for the design of the integrated circuits (IC). Three integrated circuits were designed as substrates for the integration using IBM’s 180nm and TSMC’s 65nm technology. A monolithic BAW oscillator with a resonance frequency of 1.8GHz was demonstrated with an FOM ~186dBc/Hz, comparable to other academia work. Using the developed process, a membrane BAW structure (FBAR) was integrated as well. Using a susceptor coating and zinc oxide’s (ZnO) high temperature coefficient of frequency (TCF) the device was studied as an alternative uncooled infrared sensor. Finally, a reprogrammable IC and an RF PCB were designed for volatile organic compound (VOC) testing using self-assembled monolayers (SAMs) as the absorber layer.

The miniaturization of electronics is a technique that holds a lot of potential in improving system performance in a variety of applications. The simultaneous miniaturization of sensors into the nano-scale has provided new ways to probe biological systems. Careful co-design of these electronics and sensors can unlock measurements and experiments that would otherwise be impossible to achieve. This thesis describes the design of two such instrumentation amplifiers and shows that significant gains in temporal resolution and noise performance are possible through careful optimization. A custom integrated amplifier is developed for improving the temporal resolution in nanopore recordings. The amplifier is designed in a commercial 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. A platform is then built with the amplifier at its core that integrates glass-passivated solid-state nanopores to achieve measurement bandwidth over an order of magnitude greater than the state of the art. The use of wavelet transforms for denoising the data and further improving the signal-to-noise ratio (SNR) is then explored. A second amplifier is designed in a 0.18 μm CMOS process for intracellular recordings from neurons. The amplifier contains all the compensation circuitry required for canceling the effects of the electrode non-idealities. Compared to equivalent commercial systems and the state of the art, the amplifier performs comparably or better while consuming orders of magnitude lower power. These systems can inform the design of extremely miniaturized application-specific integrated amplifiers of the future.

So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9

Ng Chong Chon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 100-103). / Abstract in English and Chinese. / 摘要 --- p.iii / Acknowledgments --- p.iv / Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- DMP Architecture --- p.6 / Chapter 2.1 --- Conventional DMP --- p.6 / Chapter 2.1.1 --- Operating Principle --- p.7 / Chapter 2.1.2 --- Disadvantages --- p.10 / Chapter 2.2 --- Pre-processing Clock Architecture --- p.10 / Chapter 2.2.1 --- Operating Principle --- p.11 / Chapter 2.2.2 --- Advantages and Disadvantages --- p.12 / Chapter 2.3 --- Phase-switching Architecture --- p.13 / Chapter 2.3.1 --- Operating Principle --- p.13 / Chapter 2.3.2 --- Advantages and Disadvantages --- p.14 / Chapter 2.4 --- Summary --- p.15 / Chapter Chapter 3 --- Full-Speed Divider Design --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Working Principle --- p.16 / Chapter 3.3 --- Design Issues --- p.18 / Chapter 3.4 --- Device Sizing --- p.19 / Chapter 3.5 --- Layout Considerations --- p.20 / Chapter 3.6 --- Input Sensitivity --- p.22 / Chapter 3.7 --- Modeling --- p.24 / Chapter 3.8 --- Review on Different Divider Designs --- p.28 / Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28 / Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30 / Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32 / Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34 / Chapter 3.9 --- Summary --- p.42 / Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43 / Chapter 4.1 --- Introduction --- p.43 / Chapter 4.2 --- Proposed DMP Topology --- p.46 / Chapter 4.3 --- Circuit Design and Implementation --- p.49 / Chapter 4.4 --- Simulation Results --- p.51 / Chapter 4.5 --- Summary --- p.53 / Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Proposed DMP Topology --- p.56 / Chapter 5.3 --- Circuit Design and Implementation --- p.59 / Chapter 5.3.1 --- Divide-by-4 stage --- p.59 / Chapter 5.3.2 --- TSPC dividers --- p.63 / Chapter 5.3.3 --- Phase-selection Network --- p.63 / Chapter 5.3.4 --- Mode-control Logic --- p.64 / Chapter 5.3.5 --- Duty-cycle Transformer --- p.65 / Chapter 5.3.6 --- Glitch Problem --- p.66 / Chapter 5.3.7 --- Phase-mismatch Problem --- p.70 / Chapter 5.4 --- Simulation Results --- p.70 / Chapter 5.5 --- Summary --- p.74 / Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75 / Chapter 6.1 --- Introduction --- p.75 / Chapter 6.2 --- Proposed DMP Architecture --- p.75 / Chapter 6.3 --- Divide-by-4 Stage --- p.76 / Chapter 6.3.1 --- Current-switch Combining --- p.76 / Chapter 6.3.2 --- Capacitive Load Reduction --- p.77 / Chapter 6.4 --- Simulation Results --- p.81 / Chapter 6.5 --- Summary --- p.83 / Chapter Chapter 7 --- Experimental Results --- p.84 / Chapter 7.1 --- Introduction --- p.84 / Chapter 7.2 --- Equipment Setup --- p.84 / Chapter 7.3 --- Measurement Results --- p.85 / Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85 / Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88 / Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93 / Chapter 7.3 --- Summary --- p.96 / Chapter Chapter 8 --- Conclusions and Future Works --- p.98 / Chapter 8.1 --- Conclusions --- p.98 / Chapter 8.2 --- Future Works --- p.99 / References --- p.100 / Publications --- p.104

One of the key building blocks in a direct-conversion receiver is the low noise amplifier (LNA), which needs to provide a sufficient gain with a low noise figure for the RF front-end. However, the wideband nature of the receiver imposes harsh requirements on the LNA. It is difficult to achieve desired performance goals over the wide frequency range without excessive power consumption. To deal with this problem, this thesis proposes a novel band-selective UWB LNA. Utilizing the frequency hopping property of the MB-OFDM system, the proposed method switches the operating frequency of the LNA in real time following the MB-OFDM's hopping pattern so that optimal gain and noise performance can be achieved in each frequency band. Unlike the conventional approach, this LNA does not need to cover the entire band simultaneously, thus excessive power consumption is avoided. Fabricated in a 0.18-mum CMOS process, the proposed LNA achieves a peak power gain of 16 dB and a minimum noise figure of 2.74 dB at a low power consumption of less than 12 mW. / Other challenges in direct-conversion MB-OFDM receivers include ultra-short band switching time and wide LO frequency range. The single-sideband (SSB) generation is an attractive method for a fast-hopping multi-band LO generator. However, it involves LO frequency synthesis in an open-loop architecture, and thus the spurious-tone performance becomes critical in maintaining the LO signal integrity. Since the accuracy of the SSB generation and the spurious-tone power are difficult to control in a high-frequency operation, a 4.5-GHz SSB upconverter system was fabricated in a standard 0.18-mum CMOS process to investigate its performance against process variation. Some precise quadrature signal generation circuits such as divider and polyphase filter are employed. Experimental results show that the fabricated SSB upconverter system achieves image rejection of higher than 48 dB and spurious-tone suppression of higher than 32 dB. / The use of an active downconversion mixer is an alternative to relax the LNA requirements for direct-conversion MB-OFDM UWB receivers. However, its linearity becomes a problem when the bandwidth is ultra wide. In this thesis, the static current bleeding technique is used in the UWB downconversion mixer to improve its linearity. By injecting a DC current to the RF transconductor for linearization, the mixer's transconductance is enhanced while the noise from the LO switches is not affected. As a result, the conversion gain increases and the noise figure improves. Fabricated in a 0.18-mum CMOS process, the UWB downconversion mixer achieves a peak conversion gain of 4.1 dB, a peak IIP3 of --2.5 dBm, and a minimum double-sideband (DSB) noise figure of 11.7 dB at a low power consumption of 6 mW. / Ultra-wideband (UWB) is a short-range, high-data-rate communication system for Wireless Personal Area Networks (WPAN) based on the IEEE 802.15.3a physical layer standard. The allocated frequency range is from 3.1 to 10.6 GHz, in which 14 bands are defined. The first band group, which is assigned to the mandatory Mode 1 devices, consists of three bands. In UWB systems, multi-band orthogonal frequency division multiplexing (MB-OFDM) is the dominant modulation scheme for its high spectral flexibility and its similarity in communication architecture with other existing wireless communication standards, such as IEEE 802.11a/b/g and WiMAX. For practical reasons, the direct-conversion architecture is widely considered the best architecture to implement an MB-OFDM UWB receiver, which has advantages of low power consumption and high integration level. Nevertheless, there are some performance limitations in direct-conversion MB-OFDM UWB receivers. In this thesis, some key building blocks in the RF front-end of the direct-conversion MB-OFDM UWB receivers for use in Mode 1 devices are investigated to overcome such limitations. / Tang, Siu Kei. / "May 2008." / Adviser: Pun Kong Pang. / Source: Dissertation Abstracts International, Volume: 70-03, Section: B, page: 1857. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (p. 161-169). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

We have investigated the structure and interfacial structure of two types of high-k dielectric thin films on Si using combined experimental and theoretical approaches. In the Hf-based high- k dielectrics, the crystallinity of three films, pure HfO2, Y-incorporated HfO2 and Al-incorporated HfO2, is examined by transmission electron diffraction (TED), and the local coordination symmetries of the Hf atoms in the films are revealed by the profile of electron energy-loss near-edge structure (ELNES) taken at oxygen K-edge. These ELNES spectra are then simulated using real-space multiple-scattering (RSMS) method. We find a good agreement between the experimental and the simulated result of pure HfO2. The incorporation of Y indeed stabilizes HfO 2 to a cubic structure, but it also contributes to possible lattice distortion and creation of complex defect states, causing discrepancies between the experimental and the simulated result. As a comparison, the local coordination symmetry of Hf is largely degraded upon the incorporation of Al, which not only amorphorizes HfO2, but also introduces significantly amount of O vacancies in the film. We have further investigated the interfacial structures of HfO2 and Al-incorporated HfO2 thin films on Si using spatially resolved ELNES, which a series of the oxygen K-edge spectra is acquired when a 0.3 nm electron probe scanning across the film/Si interface. We find that interfaces are not atomically sharp, and variation in the local coordination symmetry of Hf atoms lasts for a couple of monolayers for both the HfO2 and the Al-incorporated HfO2 samples. Annealing of the HfO2 film in the oxygen environment leads to the formation of a thick SiO2/SiOx stack layer in-between the original HfO2 and the Si substrate. As a comparison, the interfacial stability is significantly improved by incorporating Al into the HfO 2 film to form HfAlO, which effectively reduces/eliminates the interfacial silicon oxide formation during the oxygen annealing process. The interfacial structure of SiTiO3 (STO) dielectric and Si is significant different from that between Hf-based dielectric and Si, as the crystalline STO is epitaxially grown on the Si. Together with the high resolution high-angle annular-dark-field (HAADF) image, the spatially resolved ELNES acquired across the STO/Si interface reveal an amorphous interfacial region of 1-2 monolayer thickness, which is lack of Sr, but contains Ti, Si, and O. Based on these experimental evidences, we propose a classical molecular dynamic (MD) interface model, in which the STO is connected to Si by a distorted Ti-O layer and a complex Si-O layer. The simulated results, based on the MD interface model, generally agree with the experimental results, disclosing a gradual change of the local atomic coordination symmetry and possible defect incorporation at the interface. / Wang, Xiaofeng = Si衬底上高k介电薄膜的结构研究 / 王晓峰. / Adviser: Li Quan. / Source: Dissertation Abstracts International, Volume: 72-11, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 103-112). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Wang, Xiaofeng = Si chen di shang gao k jie dian bo mo de jie gou yan jiu / Wang Xiaofeng.

In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

In addition, we can further reduce the power consumption by reducing the number of interconnects. We propose to use a quaternary (4-level) logic output to replace the binary (2-level) logic output, which will reduce the number of interconnect by half. A 6-bit current mode analog-to-quaternary converter (AQC) test chip is designed with special current mode quaternary logic functions. / The power reduction techniques are carried out in both circuit and system levels. At the circuit level, a new sub-stage design using voltage comparator is proposed to reduce power consumption without any performance degradation. At the system level, we observe that the signal-to-noise ratio (SNR) of a current mode pipelined ADC is proportional to the input current level, and the SNR of a pipelined ADC is dominated by the first few stages. Thus, it is possible to reduce the power consumption without significantly degrading the SNR by gradually reducing the current level of each stage along the pipeline. A 12-bit CMOS current mode pipelined ADC test chip is designed with a 0.35mum CMOS digital process. The measured signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR) and total harmonic distortion (THD) are 64.90dB, 67.79dB and -67.02dB, respectively. The effective number of bit (ENOB) achieved is 10.49-bit and the calculated FOM is 1.31pJ, which has the lowest power consumption among reported current mode ADCs. / The supply voltage of advanced CMOS technology is reduced to 1V or less. It is very difficult to design high performance analog circuit at this supply voltage because of the limited dynamic range. One possible solution is to use current mode circuit technique which is less sensitive to the limited dynamic range. Moreover, current mode circuit is more suitable for low voltage applications compare to the conventional voltage mode circuit. This research uses analog-to-digital converter (ADC) as a vehicle to investigate current mode design techniques with a main focus on power reduction. / Chan Chi Hong. / "September 2007." / Adviser: C. F. Chan. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4923. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Leung Lai-Kan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 131-154). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Table of Contents --- p.iv / List of Figures --- p.ix / List of Tables --- p.xv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Objectives --- p.2 / Chapter 1.3 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6 / Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6 / Chapter 2.1.1 --- Cutoff frequency --- p.6 / Chapter 2.1.2 --- Center Frequency --- p.8 / Chapter 2.1.3 --- Tuning Range --- p.8 / Chapter 2.1.4 --- Tuning Sensitivity --- p.8 / Chapter 2.1.5 --- Output Power --- p.8 / Chapter 2.1.6 --- Power Consumption --- p.9 / Chapter 2.1.7 --- Supply Pulling --- p.9 / Chapter 2.2 --- Phase Noise --- p.9 / Chapter 2.2.1 --- Definition of Phase Noise --- p.9 / Chapter 2.2.2 --- Phase Noise Specification --- p.11 / Chapter 2.2.3 --- Leeson's formula --- p.12 / Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13 / Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13 / Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17 / Chapter 2.3.1 --- FETs --- p.17 / Chapter 2.3.2 --- Varactor --- p.18 / Chapter 2.3.3 --- Spiral Inductor --- p.21 / Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24 / Chapter 2.3.5 --- Analysis and Simulation --- p.26 / Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- General Principle of Oscillation --- p.28 / Chapter 3.3 --- Different Oscillator Architectures --- p.30 / Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30 / Chapter 3.3.2 --- Differential Ring Oscillator --- p.32 / Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33 / Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34 / Chapter 3.5 --- Digital Controlled Oscillator --- p.36 / Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37 / Chapter 3.6 --- Injection Locking --- p.42 / Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42 / Chapter 3.7 --- Simulation Results --- p.44 / Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44 / Chapter 3.7.2 --- Phase Noise Performance --- p.47 / Chapter 3.7.3 --- Locking Characteristics --- p.48 / Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48 / Chapter 3.8 --- Conclusion --- p.49 / Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51 / Chapter 4.1 --- Introduction --- p.51 / Chapter 4.2 --- LC Oscillator --- p.52 / Chapter 4.3 --- Circuit Design --- p.54 / Chapter 4.3.1 --- Oscillation Frequency --- p.55 / Chapter 4.3.2 --- Oscillation Amplitude --- p.58 / Chapter 4.3.3 --- Transistor Sizing --- p.59 / Chapter 4.3.4 --- Power Consumption --- p.62 / Chapter 4.3.5 --- Tuning Range --- p.62 / Chapter 4.3.6 --- Phase Noise Analysis --- p.63 / Chapter 4.4 --- Conclusion --- p.70 / Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71 / Chapter 5.1 --- Introduction --- p.71 / Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73 / Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74 / Chapter 5.3.1 --- General Explanation --- p.74 / Chapter 5.3.2 --- Mathematical Analysis --- p.75 / Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77 / Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78 / Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80 / Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83 / Chapter 5.4.3 --- Tuning Range --- p.94 / Chapter 5.4.4 --- Start-up Condition --- p.95 / Chapter 5.4.5 --- Power Consumption --- p.97 / Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98 / Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105 / Chapter 5.7 --- Conclusion --- p.108 / Chapter Chapter 6 --- Layout Consideration --- p.109 / Chapter 6.1 --- Substrate Contacts --- p.109 / Chapter 6.2 --- Guard Rings --- p.110 / Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111 / Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112 / Chapter 6.5 --- Slicing of Transistors --- p.113 / Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114 / Chapter 6.7 --- Matching of Devices --- p.114 / Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115 / Chapter Chapter 7 --- Experimental Results --- p.118 / Chapter 7.1 --- Methodology --- p.118 / Chapter 7.2 --- Evaluation Board --- p.119 / Chapter 7.3 --- Measurement Setup --- p.123 / Chapter 7.4 --- Experimental Results --- p.125 / Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125 / Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128 / Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132 / Chapter 7.5 --- Summary of Performance --- p.139 / Chapter Chapter 8 --- Conclusion --- p.142 / Chapter 8.1 --- Contribution --- p.142 / Chapter 8.2 --- Further Development --- p.143 / Chapter Chapter 9 --- Appendix --- p.145 / Chapter 9.1 --- Circuit Transformation --- p.145 / Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146 / Chapter 9.2.1 --- "Inductance," --- p.146 / Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146 / Chapter 9.2.3 --- Series Capacitance --- p.147 / Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147 / Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148 / Chapter Chapter 10 --- Bibliography --- p.151