Novel technology which can provide new solutions and enable augmented capabilities to CMOS based technology is highly desired. Piezotronic nanodevices and integrated systems exhibit potential in achieving these application goals. By combining laser interference lithography and low temperature hydrothermal method, an effective approach for ordered growth of vertically aligned ZnO NWs array with high-throughput and low-cost at wafer-scale has been developed, without using catalyst and with a superior control over orientation, location/density and morphology of as-synthesized ZnO NWs. Beyond the materials synthesis, by utilizing the gating effect produced by the piezopotential in a ZnO NW under externally applied deformation, strain-gated transistors (SGTs) and universal logic operations such as NAND, NOR, XOR gates have been demonstrated for performing piezotronic logic operations for the first time. In addition, the first piezoelectrically-modulated resistive switching device based on piezotronic ZnO NWs has also been presented, through which the write/read access of the memory cell is programmed via electromechanical modulation and the logic levels of the strain applied on the memory cell can be recorded and read out for the first time. Furthermore, the first and by far the largest 3D array integration of vertical NW piezotronic transistors circuitry as active pixel-addressable pressure-sensor matrix for tactile imaging has been demonstrated, paving innovative routes towards industrial-scale integration of NW piezotronic devices for sensing, micro/nano-systems and human-electronics interfacing. The presented concepts and results in this thesis exhibit the potential for implementing novel nanoelectromechanical devices and integrating with MEMS/NEMS technology to achieve augmented functionalities to state-of-the-art CMOS technology such as active interfacing between machines and human/ambient as well as micro/nano-systems capable of intelligent and self-sufficient multi-dimensional operations.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / This thesis is aimed at testing commercially available CMOS amplifier ICs at 4 K. Super Conducting Electronics (SCE) will also be used to amplify RSFQ signals for easier detection by CMOS technology and better signal-to-noise ratios. The SCE comprises of a Suzuki stack amplifier, a 250 μA JTL and a DC-to-SFQ converter. The Suzuki stack amplifier is simulated in WRSPICE. It is able to amplify an SFQ signal synchronised with an external clock signal. The amplified signal can then be detected by a normal commercially available CMOS amplifier IC. To keep the noise in the signal to a minimum, the commercial amplifier must be be situated as close as possible to the SCE. The amplifier must therefore be able to operate at 4 K. Ten different amplifier ICs were tested and three was found that worked down to 4 K.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis relates to the design of a camera system for a nanosatellite based on a CMOS image sensor. The design specifications and constraints are considered followed by the proposal of a versatile design with all the required functions imple- mented on a single FPGA. These functions include bad block management, data routing, an EDAC, a soft-core processor, glue logic to external devices, and com- munication busses. The Altera Nios II soft-core processor is implemented in this design, which en- ables simple changes to be made in software. A good mixture of intellectual prop- erty soft-cores, open-source cores, and user created logic are utilised in this broad base design, containing a combination of hardware, digital logic, and software. Low power and compact devices are selected for this design to minimize the power usage and the physical size of the camera system. The system's peak power consumption is 952mW which is below the required maximum consumption of 1W. This design's performance is therefore ideal for a subsystem onboard a nanosatel- lite.

Areas which require high-temperature MOS circuits are instrumentations for geothermal and petroleum well-logging, space exploration, aero-propulsion systems, and other hostile environments. MOS digital circuits at high temperature are examined as well as the maximum operating temperature of MOS devices. Factors affecting high-temperature operation of these devices, including threshold voltage sensitivity, mobility degradation, leakage current characterization and interactions, zero-TC current in analog applications and reliability considerations, are discussed. Methods to reduce threshold voltage sensitivities, process modifications to reduce leakage current density at high temperature, circuit techniques to eliminate the leakage current effects, diode compensation, CMOS thermal latch-up and MOS scaling rules at high temperature are investigated. Experimental results of epitaxial diodes to verify the leakage current reduction effect are discussed.

A new method for transient simulation of integrated circuits has been developed and investigated. The method utilizes expansion of circuit variables into Chebyshev series. A prototype computer simulation program based on this technique has been implemented and applied in the transient simulation of several MOS circuits. The results have been compared with those generated by SPICE. The method has been also combined with the waveform relaxation technique. Several algorithms were developed using the Gauss-Seidel and Gauss-Jacobi iterative procedures. The algorithms based on the Gauss-Seidel iterative procedure were implemented in the prototype software. They offer substantial CPU time savings in comparison with SPICE without compromising the accuracy of solutions. A description of the prototype computer simulation program and a summary of the results of simulation experiments are included.

The Jain and Balk analytic model for two-dimensional effects in short channel MOSFETS is investigated. The effects considered are Drain Induced Barrier Lowering, DIBL, and the maximum electric field, Emax, which influences Drain Induced High Field, DIHF. A scaled short channel design is used as the basis for the investigation. Cases are numerically simulated using the MINIMOS program. DIBL and Emax are calculated using the Jain and Balk model. Model values are compared to numerical simulation values. Results show the model consistently overestimates DIBL. Also, the range for which the model closely estimates Emax is found. Variation in Emax with change of junction depth Xj is investigated. The electric field, Ex, as it varies with depth in the channel is investigated, and compared to the Jain and Balk approximation. The deviations suggest that the model must break down for short channels.

Approved for public release, distribution is unlimited / In this thesis, SiN films grown on Si substrates were characterized using Fourier Transform Infrared (FTIR) spectroscopy. The stress in SiN films can be used to enhance of mobility of electrons and holes which increases the performance of metal-oxide-semiconductor (MOS) transistors. The samples used in this study were prepared by Applied Materials using chemical vapor deposition (CVD) technique with different growth parameters. The stress of the samples varied from 1.3 GPa compressive to 1 GPa tensile depending on the growth conditions employed. The FTIR measurement showed three distinct absorption peaks associated with Si-N, Si-H and N-H vibrational modes. The hydrogen was unintentionally incorporated into the SiN film during the CVD process due to its use as the carrier gas for the precursors. It was found from the FTIR data that the area under Si-H and N-H peaks (amount of bonds) varies in opposite directions when the film stress changes from compressive to tensile. In addition, the peak position of the Si-H absorption shifted to higher energy while the opposite was true for N-H as the stress changes from compressive to tensile. The strength and the position of the Si-N absorption peak were found to be relatively insensitive to the stress of the film. This indicates that the amount of Si-H and N-H bonds in the film is responsible for controlling the stress of the film. The use of quantum calculation of SiN molecules with different amount of Si-H and N-H bonds was used toward understanding the experimental absorption spectra. / Lieutenant, Mexican Navy

Analog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of simulation experiments. In the second phase the user is capable of modifying all the relevant circuit design parameters while directly observing the tradeoffs in the circuit performance specifications. The final design is a circuit that very closely meets a set of desired design specifications for the design parameters selected. That second phase of the proposed design methodology utilizes a graphical user interface in which the designer moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion coefficient parameters. In this dissertation there are no restrictive assumptions about the MOS transistor models. The design methodology can be used with any submicron model supported by the foundry process and in this sense the methods included within are general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As part of the design tradeoffs assessment process variations are included during the design process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS design. Process corners and the variability of the technology current are also studied and the universality of the transconductance efficiency versus inversion coefficient response is shown to be true even in the presence of process variability. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2013.

Finally, we also propose and demonstrate an integrated Mach-Zehnder optical diplexer (IMZOD) for possible use in an integrated silicon optical amplifier. The diplexer is based on two rnultimode interferometers (MMIs) and a Mach-Zehnder interferometer (MZI), and has potential use in an integrated silicon waveguide optical amplifier, to combine or separate the pump signal (1440nm) and probe signal (1556nm) for monolithic implementation of a silicon Raman amplifier. / Helium ion implantation can not only reduce the free-carrier loss, but can also enhance the detection responsivity of below-bandgap wavelengths (1440 1590 nm). We propose and demonstrate an in-line channel power monitor (ICPM) based on helium ion implanted silicon waveguides. The implanted waveguide can detect light at 1440 1590 nm which are normally not detectable by silicon. We study the enhanced photoresponse of helium ion implanted waveguide samples which were annealed at different temperatures and for different durations. / Recently there has been much interest in silicon optical amplifiers and lasers relying on stimulated Raman scattering (SRS), which, despite the much shorter waveguide lengths possible in silicon compared with silica optical fiber, can still provide large optical gain because of the large Raman coefficient of silicon and small mode field areas. However, two-photon absorption (TPA) generated free-carrier absorption (FCA) loss can exceed the Raman gain. In this thesis, experiments and theoretical model will he discussed and analyzed, showing that helium ion implantation can successfully reduce the optical losses due to free-carriers and allow net gain to be attained by continuous-wave (CW)-pumped SRS without requiring external bias to remove the photo-generated free carriers. The theoretical study of dynamics of free carrier lifetime of the silicon waveguides will be described. The effective nonlinear length of the silicon waveguides is defined and studied. The theoretical and experimental studies of the enhanced spectral broaden induced by self-phase-modulation (SPM) are carried out in helium on implanted silicon waveguides. / Silicon-on-insulator (SOI) wafers are an attractive platform for the fabrication of planar lightwave circuits (PLCs) because they offer the potential for low-cost fabrication using mature complementary metal--organic--semiconductor (CMOS) compatible processes developed in the microelectronics industry. At the wavelengths of interest for telecommunications, SOI waveguides can have low optical losses (0.1dB/cm). Besides, the strong optical confinement offered by the high index contrast between silicon (Si) (n=3.45) and silicon dioxide (SiO2) (n=1.45) makes it possible to scale photonic devices to sub-micron level. In addition, the high optical intensity arising from the strong optical confinement inside the waveguide makes it possible to observe nonlinear optical effects, such as Raman and Kerr effects, in chip-scale devices. / We then make use of the ICPM to perform a system application, called optical-burst-and-transient-equalizer (OBTE). The OBTE may provide a compact and low-cost solution to compensate gain-transient, gain-spectrum-tilt and to equalize the upstream packet amplitude in erbium doped fiber amplifier (EDFA) amplified hybrid dense-wavelength-division-multiplexed (DWDM) and time-division-multiplexed (TDM) passive-optical-networks (PONs). The OBTE may be monolithically integrated on SOI platform and is potentially low cost and compact. The OBTE can compensate complicated gain slope shape, which may be generated in cascaded EDFAs or deliberate channel add/drop, based on individual channel equalization. 15-dB receiver sensitivity improvement at 10 Gbit/s bit-error-rate (BER) measurements of 10-9 was achieved by the compensation. / Liu, Yang. / "August 2007." / Adviser: Hon Ki Tsang. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1212. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.

For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition. / In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters. / Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process. / The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed. / Au Yeung, Chung Fai. / "August 2007." / Adviser: Chang Kwok Keung. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 153-161). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.