Field-effect transistor technologies have been critical building blocks for satellite systems since their introduction into the microelectronics industry. The extremely high cost of launching payloads into orbit necessitates systems to have small form factor, ultra low-power consumption, and reliable lifetime operation, while satisfying the performance requirements of a given application. Silicon-based complementary metal-oxide-semiconductors (Si CMOS) have traditionally been able to adequately meet these demands when coupled with radiation hardening techniques that have been developed over years of invested research. However, as customer demands increase, pushing the limits of system throughput, noise, and speed, alternative technologies must be employed. Silicon-germanium BiCMOS platforms have been identfied as a technology candidate for meeting the performance criteria of these pioneering satellite systems and deep space applications, contingent on their ability to be hardened to radiation-induced damage. Given that SiGe technology is a relative new- comer to terrestrial and extra-terrestrial applications in radiation-rich environments, the same wealth of knowledge of time-tested radiation hardening methodologies has not been established as it has for Si CMOS. Although SiGe BiCMOS technology has been experimentally proven to be inherently tolerant to total-ionizing dose damage mechanism, the single event susceptibility of this technology remains a primary concern. The objective of this research is to characterize the physical mechanisms that drive the origination of ion-induced transient terminal currents in SiGe HBTs that subsequently lead to a wide range of possible single event phenomena. Building upon this learning, a variety of device-level hardening methodologies are explored and tested for efficacy.

A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders of magnitude smaller than the conventional static CMOS gates ). The design of a decimation filter using novel Multi-Rate systolic architecture and it's implementation in Folded Source-Coupled Logic is also considered. The decimation filter thus designed can be used in mixed-mode applications like Sigma-Delta A/D converter to improve it's performance characteristics like dynamic range, resolution and phase linearity at higher sampling rates. / Graduation date: 1992

The advent of high-frequency silicon-based technologies has enabled the design of mixed-signal circuits that incorporate analog, RF, and digital circuit components to build cost-effective system-on-a-chip solutions. Emerging applications provide great incentive for continued scaling of transistor performance, requiring careful attention to mismatch, noise, and reliability concerns. If these mixed-signal technologies are to be employed within space-based electronic systems, they must also demonstrate reliability in radiation-rich environments. SiGe BiCMOS technology in particular is positioned as an excellent candidate to satisfy all of these requirements. The objective of this research is to develop predictive modeling tools that can be used to design new mixed-signal technologies and assess their reliability on Earth and in extreme environments. Ultimately, the goal is to illuminate the interaction of device- and circuit-level reliability mechanisms and establish best practices for modeling these effects in modern circuits. To support this objective, several specific areas have been targeted first, including a TCAD-based approach to identify performance-limiting regions in SiGe HBTs, measurement and modeling of carrier transport parameters that are essential for predictive TCAD, and measurement of device-level single-event transients to better understand the physical origins and implications for device design. These tasks provide the foundation for the bulk of this research, which addresses circuit-level reliability challenges through the application of novel mixed-mode TCAD techniques. All of the individual tasks are tied together by a guiding theme: to develop a holistic understanding of the challenges faced by emerging broadband technologies by coordinating results from material, device, and circuit studies.

This work evaluates two SiGe BiCMOS technology platforms as candidates for implementing extreme environment capable circuitry, with an emphasis on applications requiring high sensitivity and low noise. In Chapter 1, applications requiring extreme environment sensing circuitry are briefly reviewed and the motivation for undertaking this study is outlined. A case is then presented for the use of SiGe BiCMOS technology to meet this need, documenting the benefits of operating SiGe HBTs at cryogenic temperatures. Chapter 1 concludes with a brief description of device radiation effects in bipolar and CMOS devices, and a basic overview of noise in semiconductor devices and electronic components. Chapter 2 further elaborates on a specific application requiring low-noise circuitry capable of operating at cryogenic temperatures and proposes a number of variants of band-gap reference circuits for use in said system. Detailed simulation and theoretical analysis of the proposed circuits are presented and compared with measurements, validating the techniques used in the proposed designs and emphasizing the need for further understanding of device level low-temperature noise phenomena. Chapter 3 evaluates the feasibility of using a SiGe BiCMOS process, whose response to ionizing radiation was previously uncharacterized, for use in unshielded electronic systems needed for exploration of deep space planets or moons, specifically targeting Europa mission requirements. Measured total ionizing dose (TID) responses for both CMOS and bipolar SiGe devices are presented and compared to similar technologies. The mechanisms responsible for device degradation are outlined, and an explanation of unexpected results is proposed. Finally, Chapter 4 summarizes the work presented and understanding provided by this thesis, concluding by outlining future research needed to build upon this study and fully realize SiGe based extreme environment capable precision electronic systems.

With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for video signals as well as signal conditioning filters in high speed communication channels are examples of applications where high frequency integrated circuits are now feasible. Transconductance-Capacitor or Gm-C filters are well suited to these applications as they operate in the continuous-time domain and are able to overcome the high-frequency and noise limitations imposed by clocked filter topologies. This thesis covers the design of a programmable fourth-order Chebychev filter with a 50MHz passband using the transconductance-C technique. A previously proposed transconductor based upon a CMOS inverter is used to implement the filter. Since this transconductor has no internal nodes, it can achieve extremely high bandwidths. However, it requires a variable power source for programming. Thus, a wide-band, on-chip, variable-BiCMOS power supply is presented as the method for setting the transconductance. Practical design issues are addressed as well as many methods for compensating non-idealities. Simulations of the filter as well as some parametric measurement of the filter structures are presented. / Graduation date: 1994

In the last two decades, VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm, achieving higher performance and packing more complex functionalities into digital integrated circuits have become easier. However, the scaling trend poses new challenges to design and process engineers. First, larger process parameter variations in the current technologies cause larger spread in the delay and power distribution of circuits and result in the parametric yield loss. In addition, ensuring the reliability of deep sub-micron (DSM) technologies under soft/transient errors is a significant challenge. These errors occur because of the combined effects of the atmospheric radiations and the significantly reduced noise margins of scaled technologies. This thesis focuses on addressing the issues related to the process variations and reliability in deeply scaled CMOS technologies. The objective of this research has been to develop circuit-level techniques to address process variations, transient errors, and the reliability concern. The proposed techniques can be divided into two parts. The first part addresses the process variation concern and proposes techniques to reduce the variation effects on power and performance distribution. The second part deals with the transient errors and techniques to reduce the effect of transient errors with minimum hardware or computational overhead.

Motivated by the necessity to consider probabilistic approaches to future designs, the main objective of this thesis was to develop and characterize energy efficient probabilistic CMOS (PCMOS) circuits that can be used to implement low energy computing platforms. The simplest circuit characterized was a PCMOS inverter (switch). An analytical model relating the energy consumption per switching (E) of this switch to its probability of correctness, p was derived. This characterization can also be used to evaluate the energy and performance savings that are achieved by PCMOS switch based computing platforms. The characterization of a PCMOS inverter was also extended to larger circuits whose probabilistic behavior was analyzed by first developing probability models of primitive gates, which were then input to a graph-based model to find the probabilities of larger circuits. The analysis of larger probabilistic circuits provides a basis for analyzing probabilistic behaviors due to noise in future technologies, and can be used in probabilistic design and synthesis methods to improve circuit reliability. Another important design criterion is the speed of a PCMOS circuit. The trade-offs between the energy, speed, and p of PCMOS circuits were also analyzed. Based on this study, various methods were proposed to optimize energy delay product (EDP) and p under given constraints on p, performance, and EDP. The sensitivity of the analysis with respect to variations in temperature, supply voltage, and threshold voltage was also considered.

This research focuses on the implementation of the efficient image compression system among the many potential applications of a transform imager system. The study includes implementing the image compression system using a transform imager, developing a novel image compression algorithm for the system, and improving the performance of the image compression system through efficient encoding and decoding algorithms for vector quantization. A transform imaging system is implemented using a transform imager, and the baseline JPEG compression algorithm is implemented and tested to verify the functionality and performance of the transform imager system. The computational reduction in digital processing is investigated from two perspectives, algorithmic and implementation. Algorithmically, a novel wavelet-based embedded image compression algorithm using dynamic index reordering vector quantization (DIRVQ) is proposed for the system. DIRVQ makes it possible for the proposed algorithm to achieve superior performance over the embedded zero-tree wavelet (EZW) algorithm and the successive approximation vector quantization (SAVQ) algorithm. However, because DIRVQ requires intensive computational complexity, additional focus is placed on the efficient implementation of DIRVQ, and highly efficient implementation is achieved without a compromise in performance.

In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.

The objective of this work is to investigate the performance of SiGe HBTs and scaled CMOS devices in extreme environments. In this work, the inverse mode operation of SiGe HBTs is investigated as a potential solution to the vulnerability of SiGe HBTs to single event effects. The performance limitations of SiGe HBTs operating in inverse mode are investigated through an examination of the effects of scaling on inverse mode performance and optimization schemes for inverse mode performance enhancements are discussed and demonstrated. In addition the performance of scaled MOSFETs, that constitute the digital backbone of any BiCMOS technology, is investigated under radiation exposure and cryogenic temperatures. Extreme environments and their effects on semiconductor devices are introduced in Chapter 1. The immunity of 90nm MOSFETs to total ionizing dose damage under proton radiation is demonstrated. Inverse mode operation of SiGe HBTs is introduced in Chapter 2 as a potential radiation hard solution by design. The effect of scaling on inverse mode performance of SiGe HBTs is investigated and the performance limitations in inverse mode are identified. Optimization schemes for improving inverse mode performance of SiGe HBTs are discussed in Chapter 3. Inverse mode performance enhancement is demonstrated experimentally in optimized device structures manufactured in a commercial third generation SiGe HBT BiCMOS platform. Further, a cascode device structure, the combines the radiation immunity of an inverse mode structure with the performance of a forward mode common emitter device is XIV discussed. Finally, idealized doping profiles for inverse mode performance enhancement is discussed through TCAD simulations. The cryogenic performance of inverse mode SiGe HBTs are discussed in Chapter 4. A novel base current behavior at cryogenic temperature is identified and its effect on the inverse mode performance is discussed. Matching performance of a 90nm bulk CMOS technology at cryogenic temperatures is investigated experimentally and through TCAD simulations in Chapter 5. The effect of various process parameters on the temperature sensitivity of threshold voltage mismatch is discussed. The potential increase of mismatch in subthreshold MOSFETs operating in cryogenic temperatures due to hot carrier effects is also investigated.