Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

The continual downscaling of the thickness of the SiO₂ layer in the complementary metal oxide semiconductor (CMOS) transistors has been one of the main driving forces behind the growth of the semiconductor industry for past 20-30 years. The gate dielectric works as a capacitor and therefore the reduction in thickness results in increase of capacitance and the speed of the device. However, this process has reached the limit when the further reduction of the SiO₂ thickness will result in a leakage current above the acceptable limit, especially for mobile devices. This problem can be resolved by replacing SiO₂ with materials which have higher dielectric constants (high-k). The leading candidates to replace SiO₂ as a gate material are hafnium dioxide and hafnium silicate. However, several problems arise when using these materials in the device. One of them is to find p and n type gate metals to match with the valence and conduction band edges of silicon. This problem can be rooted in lack of our understanding of the band alignment and its controlling mechanisms between the materials in the gate stack. Theoretical simulations using density functional theory can be very useful to address such problems. In this dissertation present a theoretical study of the band alignment between HfO₂ and SiO₂ interface. We identify oxygen coordination as a governing factor for the band alignment. Next, we discuss effects of Al incorporation on the band alignment at the SiO₂/HfO₂ interface. We find that one can tune the band alignment by controlling the concentration of Al atoms in the stack. We also perform a theoretical study of HfO₂/Metal interface in case of Rh. We identify Rh as a good candidate for a p-type gate metal due to its large work-function and the low oxidation energy. Finally, we report a study of the stability of oxygen vacancies across the gate stack. We model a gate stack composed of n-Si/SiO₂/HO₂/Rh. We find that oxygen vacancies are easier to create in SiO₂ than in HfO₂. Also, vacancies in HfO₂ modify the band alignment, while in SiO₂ they have no effect. / text

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We present a theoretical study of the electronic structure, surface energies and work functions of orthorhombic Pt monosilicide and germanides of Pt, Ni, Y and Hf within the framework of density functional theory (DFT). Calculated work functions for the (001) surfaces of PtSi, NiGe and PtGe suggest that these metals and their alloys can be used as self-aligned contacts to p-type silicon and germanium. In addition, we also study electronic structure and calculate the Schottky-barrier height at Si(001)/PtSi(001) interface and GaAs(001)/NiPtGe(001) interfaces with different GaAs(001) and NiPtGe (001) terminations. The p-type Schottky barrier height of 0.28 eV at Si/PtSi interface is found in good agreement with predictions of a simple metal induced gap states (MIGS) theory and available experiment. This low barrier suggests PtSi as a low contact resistance junction metal for silicon CMOS technology. We identify the growth conditions necessary to stabilize this orientation. The calculated p-type Schottky barrier heights (SBH) at different GaAs/NiPtGe interfaces vary by as much as 0.18 eV around the average value of 0.5 eV. We further identify and discuss factors responsible for strong Fermi level pinning resulting in small variation in the p-SBH. We also present a theoretical study of magnetic state of [beta]-MaAs and show that it is antiferromagnetic and explain the lack of observed long-range order.

The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility. / text