Miniaturization and functionality have always governed advances in electronic system technology. To truly achieve the goal of a multi mega-functional system, advances must be made not just at the IC level, but at the system level too. This concept of tighter integration at the system level is called System-on-Package (SOP). While SOP has a wide range of applications, this work targets the mobile application space. The main driver in the mobile application space is package profile. Reduction in thickness is very critical for enabling next-generation ultra-high density mobile products. In order to pack more functionality into a smaller volume, it is absolutely imperative that package profiles are reduced. The NEMI roadmap projects that the package profile should be reduced to 200µm from the current 500µm by 2014. This work attempts to demonstrate the feasibility of ultra-thin substrates (<200µm) using a new advanced material system tailored for high-frequency mobile applications. The main barriers to adoption of thin substrates include processing challenges, concerns about via and through hole reliability and warpage. Each of these factors is studied and a full-fledged test vehicle built to demonstrate the reliability of thin substrates using the advanced low-loss RXP-4/RXP-1 material system. Finite element models are developed to provide an understanding of the factors that affect the reliability of these substrates. Finally, IC assembly is demonstrated on these substrates.

Consumer demands are driving the current trend in the microelectronics industry to make electronic products that are miniature, fast, compact, high-density, reliable and low-cost. The use of surface mount devices (SMDs) has helped to decrease the size of electronic packages through the use of solder bump interconnections between the devices and the substrates/printed wiring boards (PWBs). Solder bumps act as not only mechanical, but also electrical interconnections between the device and the substrate/PWB. Common manufacturing defects ¨C such as open, cracked, missing, and misaligned solder bumps ¨C are difficult to detect because solder bumps are hidden between the device and the substrate/PWB after assembly. The reliability of packaged electronic devices in storage and usage is a major concern in the microelectronics industry. Therefore, quality inspection of solder bumps has become a critical process in the microelectronics industry to help ensure product quality and reliability. In this thesis, a methodology for quality evaluation and reliability study of solder bumps in electronic packages has been developed using the non-destructive and non-contact laser ultrasound-interferometric technique, finite element and statistical methods in this research work. This methodology includes the following aspects: 1) inspection pattern ¨C specific inspection patterns are created according to inspection purpose and package formats, 2) laser pulse energy density calibration ¨C specific laser pulse power and excitation laser spot size are selected in terms of package formats, 3) processing and analysis methods, including integrated analytical, finite element and experimental modal analyses approach, advanced signal processing methods and statistical analysis method, 4) approach combining modal analysis and advanced signal processing to improve measurement sensitivity of laser ultrasound-interferometric inspection technique, and 5) calibration curve using energy based simulation method and laser ultrasound inspection technique to predict thermomechanical reliability of solder bumps in electronic packages. Because of the successful completion of the research objectives, the system has been used to evaluate a broad range of solder bump defects in a variety of packaged electronic devices. The development of this system will help tremendously to improve the quality and reliability of electronic packages.

Microelectronic systems packaging involves layout dimensions of the order of microns. During manufacturing, process variations will cause parameters to deviate from their nominal values. As a result, the manufactured circuit may no longer meet the specifications it is designed to satisfy. When producing high volume of electronics, assembly yield becomes very important. This is where tolerance margins of the design parameters play an important role. This means that the performance specifications should be satisfied if the process variations are within the given tolerance margin of design parameters. Research has been done on circuit level design for manufacturability methods. The main objective of the research is to study the layout level DFM methods for signal integrity issues and embedded Rf passive components and use design centering methodology to improve the output yield value. In this dissertation, emphasis is also laid on taking care of the regression error while calculating the yield value. With the developed method, the number of design iteration cycles to maximize yield is significantly reduced.

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008. / Includes bibliographical references.

Thesis (Ph. D.)--Chemistry and Biochemistry, Georgia Institute of Technology, 2008. / Committee Chair: Dr. C. P. Wong; Committee Member: Dr. Boris Mizaikoff; Committee Member: Dr. Rigoberto Hernandez; Committee Member: Dr. Z. John Zhang; Committee Member: Dr. Z.L. Wang.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2007. / Includes bibliographical references.