Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.

Multi-layered electronic packages increase in complexity with demands for functionality. Interfacial delamination remains a prominent failure mechanism due to mismatch of coefficient of thermal expansion (CTE). Numerous studies have investigated interfacial cracking in microelectronic packages using fracture mechanics, which requires knowledge of starter crack locations and crack propagation paths. Cohesive zone theory has been identified as an alternative method for modeling crack propagation and delamination without the need for a pre-existing crack. In a cohesive zone approach, traction forces between surfaces are related to the crack tip opening displacement and are governed by a traction-separation law. Unlike traditional fracture mechanics approaches, cohesive zone analyses can predict starter crack locations and directions or simulate complex geometries with more than one type of interface. In a cohesive zone model, cohesive zone elements are placed along material interfaces. Parameters that define cohesive zone behavior must be experimentally determined to be able to predict delamination propagation in a microelectronic package. The objective of this work is to study delamination propagation in a copper/mold compound interface through cohesive zone modeling. Mold compound and copper samples are fabricated, and such samples are used in experiments such as four-point bend test and double cantilever beam test to obtain the cohesive zone model parameters for a range of mode mixity. The developed cohesive zone elements are then placed in a small-outline integrated circuit package model at the interface between an epoxy mold compound and a copper lead frame. The package is simulated to go through thermal profiles associated with the fabrication of the package, and the potential locations for delamination are determined. Design guidelines are developed to reduce mold compound/copper lead frame interfacial delamination.

The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ~35% and ~65%, respectively, in tensile strength (~0.8 GPa) and modulus (~90 GPa) during tensile testing; an ~20% improvement in electrical conductivity (~80000 S m⁻¹) was also reported. The mechanism of the microwave response of CNTs was discussed. Such an microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ~30 mm² s⁻¹ along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ~27 and ~540 W m⁻¹ K⁻¹, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ~1×10⁻⁷ m² K W⁻¹. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.

Microelectronic systems are subjected to thermal cycling, power cycling, and vibration environments in various applications. These environments, whether applied sequentially or simultaneously, affect the solder joint reliability. Literature is scarce on predicting solder joint fatigue failure under such multiple loading environments. This thesis aims to develop a unified modeling methodology to study the reliability of electronic packages subjected to thermal cycling, power cycling, and vibration loading conditions. Such a modeling methodology is comprised of an enriched material model to accommodate time-, temperature-, and direction-dependent behavior of various materials in the assembly, and at the same time, will have a geometry model that can accommodate thermal- and power-cycling induced low-cycle fatigue damage mechanism as well as vibration-induced high-cycle fatigue damage mechanism. The developed modeling methodology is applied to study the reliability characteristics of ceramic area array electronic packages with lead-based solder interconnections. In particular, this thesis aims to study the reliability of such solder interconnections under thermal, power, and vibration conditions individually, and validate the model against these conditions using appropriate experimental data either from in-house experiments or existing literature. Once validated, this thesis also aims to perform a design of simulations study to understand the effect of various materials, geometry, and thermal parameters on solder joint reliability of ceramic ball grid array and ceramic column grid array packages, and use such a study to develop universal polynomial predictive equations for solder joint reliability. The thesis also aims to employ the unified modeling methodology to develop new understanding of the acceleration factor relationship between power cycling and thermal cycling. Finally, this thesis plans to use the unified modeling methodology to study solder joint reliability under the sequential application of thermal cycling and vibration loading conditions, and to validate the modeling results with first-of-its-kind experimental data. A nonlinear cumulative damage law is developed to account for the nonlinearity and effect of sequence loading under thermal cycling, power cycling, and vibration loading.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

The demands of consumer electronic products to support multi-functionality such as computing, communication and multimedia applications with reduced form factor and low cost is the driving force behind packaging technologies such as System on Package (SOP). SOP aims to enhance the functionality of the package while providing form factor reduction by the integration of active and passive components. However, embedding components within mixed signal packages causes unwanted interferences across the digital and analog-radio frequency (RF) sections of the package, which is a major challenge yet to be addressed. This dissertation focused on the chip-last method of embedding chips within cavities in organic packages and addressed the challenges for preserving power integrity in such packages. The challenges associated with electromagnetic coupling in packages when chips are embedded within the substrate layers are identified, analyzed and demonstrated. The presence of the chip embedded within the package introduces new interaction mechanisms between the chip and package that have not been encountered in conventional packages with surface mounted chips. It is of significant importance to understand the chip-package interaction mechanisms, for ensuring satisfactory design of systems with embedded actives. The influence of the electromagnetic coupling from the package on the bulk substrate and bond-pads of the embedded chip are demonstrated. Solutions that remedy the noise coupling using Electromagnetic Band-Gap structures (EBGs) along with design methodologies for their efficient implementation in multilayer packages are proposed. This dissertation presents guidelines for designing efficient power distribution networks in multilayer packages with embedded chips.

Title from PDF of title page. / Document formatted into pages; contains 87 pages. / Thesis (M.S.M.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: As technology progresses towards smaller electronic packages, thermo-mechanical considerations pose a challenge to package designers. One area of difficulty is the ability to predict the fatigue life of the solder connections. To do this one must be able to accurately model the thermo-mechanical performance of the electronic package. As the solder ball size decreases, it becomes difficult to determine the performance of the package with traditional methods such as the use of strain gages. This is due to the fact that strain gages become limited in size and resolution and lack the ability to measure discreet strain fields as the solder ball size decreases. A solution to the limitations exhibited in strain gages is the use of Moiré interferometry. Moiré interferometry utilizes optical interferometry to measure small, in-plane relative displacements and strains with high sensitivity. / ABSTRACT: Moiré interferometry is a full field technique over the application area, whereas a strain gage gives an average strain for the area encompassed by the gage. This ability to measure full field strains is useful in the analysis of electronic package interconnections; especially when used to measure strains in the solder ball corners, where failure is known to originate. While the improved resolution of the data yielded by the method of Moiré interferometry results in the ability to develop more accurate models, that is not to say the process is simple and without difficulties of it's own. Moiré interferometry is inherently susceptible to error due to experimental and environmental effects; therefore, it is vital to generate a reliable experimental procedure that provides repeatable results. This was achieved in this study by emulating and modifying established procedures to meet our specific application. / ABSTRACT: The developed procedure includes the preparation of the specimen, the replication and transfer of the grids, the use of the PEMI, interpretation of results, and validation of data by finite element analysis using ANSYS software. The data obtained maintained uniformity to the extent required by the scope of this study, and potential sources of error have been identified and should be the subject of further research. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

The current trend in electronics manufacturing is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, mismatches in the thermomechanical properties of materials used can lead to warpage, hindering these goals. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize isotropic volume averaging to estimate effective material properties in layers of copper mixed with interlayer dielectric material. However, these estimates do not provide material properties with sufficient accuracy to predict warpage, as they contain no information about the orientation of the copper traces. This thesis describes the development of a new technique to predict the warpage of a particular substrate. The technique accounts for both the trace pattern planar density and planar orientation in determining effective orthotropic material properties for each layer of a multi-layer substrate. Starting with the trace pattern image, this technique first divides the trace pattern into several smaller areas for a given layer of the substrate and then uses image processing techniques to determine the copper percentage and average trace orientation in each small area. The copper percentage and average trace direction orientation are used in conjunction with the material properties of copper and the dielectric material to calculate the effective orthotropic material properties of each smaller area of the substrate. A finite-element model is then created where each layer is represented as a concatenation of several small areas with independent directional properties, and such a model is then subjected to sequential thermal excursion as seen in the actual fabrication process. The results from the models have been compared against experimental data with a great degree of accuracy. The modeling technique and the results obtained clearly demonstrate the need for the proposed subdivisional orthotropic material property calculations, as opposed to homogeneous isotropic properties typically used for each layer in computational simulations, as these more accurate directional properties are capable of predicting warpage with higher accuracy.