Spelling suggestions: "subject:"ttf"" "subject:"mttf""
1 |
Maintenance, a Forgotten Part of the Strategic Plan / Maintenance, a Forgotten Part of the Strategic PlanRiva Zaferson, Franco Alberto 03 August 2018 (has links)
This article exposes the reasons behind the relegation of maintenance management as an operative unit instead of a strategic tool in the organizational management. It works with literature review and the peruvian business context. Finally, it shows some statistical criteria relevant to the maintenance planning. / En el artículo se expone los motivos por los cuales la gestión de mantenimiento ha sido relegada a una unidad operativa en lugar de ser tomada en cuenta como herramienta estratégica de la gestión organizacional. Se trabaja con relación a revisión de literatura y a la situación del empresariado peruano. Finalmente se exponen algunos criterios estadísticos que pueden ser relevantes al momento de planificar el mantenimiento.
|
2 |
Estimating the expected latency to failure due to manufacturing defectsDorsey, David Michael 30 September 2004 (has links)
Manufacturers of digital circuits test their products to find defective parts so they are not sold to customers. Despite extensive testing, some of their products that are defective pass the testing process. To combat this problem, manufacturers have developed a metric called defective part level. This metric measures the percentage of parts that passed the testing that are actually defective. While this is useful for the manufacturer, the customer would like to know how long it will take for a manufacturing defect to affect circuit operation. In order for a defect to be detected during circuit operation, it must be excited and observed at the same time. This research shows the correlation between defect detection during automatic test pattern generation (ATPG) testing and normal operation for both combinational and sequential circuits. This information is then used to formulate a mathematical model to predict the expected latency to failure due to manufacturing defects.
|
3 |
The Study of Lifetime Prediction and Reliability Test of Co-Chromaticity Glass and Silicone PhosphorLiou, Jyun-Sian 04 August 2011 (has links)
A Ce:YAG-doped glass phosphor layer instead of conventional Ce:YAG-doped silicone phosphor layer as phosphor-converted white-light emitting diodes (PC-WLEDs) is demonstrated. The advantage of employing doped glass encapsulation in high power PC-WLEDs could be explained the material property of glass transition temperature of 750¢J was higher than silicone of 150¢J.
The lumen degradation, chromaticity shift, color temperature change, transmittance, and fluorescence spectrum in glass and silicone based high-power PC-WLEDs under thermal aging at 150¢J, 200¢J, and 250¢J is compared and presented. Under highest temperature of 250¢J, the glass and silicone encapsulation base d PC-WLEDs exhibited 8.15% and 38.85% in lumen loss, 1.07 and 7.32 in chromaticity shift, 856 K and 3666 K in color temperature change, 4.21% and 28.1% in transmittance loss, respectively. However, the excitation spectrum altered as slight as emission spectrum before and after experiments.
After aging test, the mean-time-to-failure (MTTF) evaluation of glass and silicone encapsulation materials for PC-WLEDs in accelerated thermal tests is also compared and presented by the using of Weibull distribution and Arrhenius equation. The MTTF of PC-WLEDs is defined the lumen decayed to 90%. The results showed that the glass as encapsulation material of PC-WLEDs exhibited higher MTTF than the silicone encapsulation by about 4.81, 5.92, and 7.53 times in lumen loss at 150¢J, 200¢J, and 250¢J, respectively.
The results of the lumen loss, chromaticity shift, and MTTF investigations demonstrated that the thermal-stability performance of the glass based PC-WLEDs were better than silicone based PC-WLEDs at 150¢J, 200¢J, and 250¢J. A better thermal stability phosphor layer of glass as encapsulation material may be beneficial to the many applications where the LED modules with high power and high reliability are demanded.
|
4 |
Estimating the expected latency to failure due to manufacturing defectsDorsey, David Michael 30 September 2004 (has links)
Manufacturers of digital circuits test their products to find defective parts so they are not sold to customers. Despite extensive testing, some of their products that are defective pass the testing process. To combat this problem, manufacturers have developed a metric called defective part level. This metric measures the percentage of parts that passed the testing that are actually defective. While this is useful for the manufacturer, the customer would like to know how long it will take for a manufacturing defect to affect circuit operation. In order for a defect to be detected during circuit operation, it must be excited and observed at the same time. This research shows the correlation between defect detection during automatic test pattern generation (ATPG) testing and normal operation for both combinational and sequential circuits. This information is then used to formulate a mathematical model to predict the expected latency to failure due to manufacturing defects.
|
5 |
Estudo sobre modelagem e avaliação de confiabilidade em redes óticasSantana, Wallace Rodrigues de January 2010 (has links)
Orientador: Prof. Dr. Guiou Kobayashi. / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-graduação em Engenharia de Informação, 2010 / Nos dias de hoje, as redes de comunicação têm se mostrado cada vez mais vitais e importantes, pois provêm conexões locais, regionais e internacionais para voz, dados e vídeo. Num mundo globalizado, elas desempenham um papel importante na economia e nas relações humanas, de tal maneira que a sua indisponibilidade, ainda que por pouco tempo, pode causar uma série de transtornos e inconvenientes. As redes de comunicação são baseadas principalmente em enlaces de fibra ótica, que estão distribuídas geograficamente, enterradas ao longo de rodovias, ferrovias, junto a gasodutos e oleodutos, e por conseqüência, expostas aos mais variados tipos de sinistros que podem acarretar a sua
indisponibilidade, como escavações, enchentes, terremotos, falhas humanas, falhas de equipamento, etc. Assim, este trabalho procura discutir e apresentar uma metodologia para modelar e avaliar a confiabilidade das redes óticas, de modo a construir um modelo de confiabilidade que possa ser usado por provedores de serviços para adequar suas operações aos acordos de níveis de serviço estabelecidos com seus clientes. / Nowadays, communication networks have proved increasingly vital and important as they
come from local connections, regional and international voice, data and video. In a globalized world, they play an important role in the economy and human relationships, so that its unavailability, even for a short time, can cause a lot of trouble and inconvenience.
Communication networks are mainly based on optical fiber links, which are distributed
geographically, buried along highways, railways, along with gas and oil pipelines, and consequently exposed to all kinds of accidents which may lead to its unavailability, as excavations, floods, earthquakes, human error, equipment failures, etc. Thus, this paper discusses and presents a methodology to model and evaluate the reliability of
optical networks in order to construct a model of reliability that can be used by service providers to tailor their operations to service level agreements established with their customers.
|
6 |
Reliability Engineering Approach to Probabilistic Proliferation Resistance Analysis of the Example Sodium Fast Reactor Fuel Cycle FacilityCronholm, Lillian Marie 2011 August 1900 (has links)
International Atomic Energy Agency (IAEA) safeguards are one method of proliferation resistance which is applied at most nuclear facilities worldwide. IAEA safeguards act to prevent the diversion of nuclear materials from a facility through the deterrence of detection. However, even with IAEA safeguards present at a facility, the country where the facility is located may still attempt to proliferate nuclear material by exploiting weaknesses in the safeguards system. The IAEA's mission is to detect the diversion of nuclear materials as soon as possible and ideally before it can be weaponized. Modern IAEA safeguards utilize unattended monitoring systems (UMS) to perform nuclear material accountancy and maintain the continuity of knowledge with regards to the position of nuclear material at a facility. This research focuses on evaluating the reliability of unattended monitoring systems and integrating the probabilistic failure of these systems into the comprehensive probabilistic proliferation resistance model of a facility.
To accomplish this, this research applies reliability engineering analysis methods to probabilistic proliferation resistance modeling. This approach is demonstrated through the analysis of a safeguards design for the Example Sodium Fast Reactor Fuel Cycle Facility (ESFR FCF).
The ESFR FCF UMS were analyzed to demonstrate the analysis and design processes that an analyst or designer would go through when evaluating/designing the proliferation resistance component of a safeguards system. When comparing the mean time to failure (MTTF) for the system without redundancies versus one with redundancies, it is apparent that redundancies are necessary to achieve a design without routine failures.
A reliability engineering approach to probabilistic safeguards system analysis and design can be used to reach meaningful conclusions regarding the proliferation resistance of a UMS. The methods developed in this research provide analysts and designers alike a process to follow to evaluate the reliability of a UMS.
|
7 |
Hardware and Software Fault-Tolerance of Softcore Processors Implemented in SRAM-Based FPGAsRollins, Nathaniel Hatley 09 March 2012 (has links) (PDF)
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at great spatial cost. To reduce the spatial cost, terrestrial ASIC-based processor protection techniques are applied to the LEON3 processor. These techniques come at the cost of time instead of area. The software fault-tolerance techniques used to protect the logic and routing of the LEON3 softcore processor include a modified version of software implemented fault tolerance (SWIFT), consistency checks, software indications, and checkpointing. To measure the reliability of a mitigated LEON3 softcore processor, an updated hardware fault-injection model is created, and novel reliability metrics are employed. The improvement in reliabilty over an unmitigated LEON3 is measured using four metrics: architectural vulnerability factor (AVF), mean time to failure (MTTF), mean useful instructions to failure (MuITF), and reliability-area-performance (RAP). Traditional reliability techniques provide the best reliability: DWC with checkpointing improves the MTTF and MuITF by almost 35x and TMR with triplicated input and outputs improves the MTTF and MuITF by almost 6000x. Software fault-tolerance provides significant reliability for a much lower area cost. Each of these techniques provides greater processor protection than a popular state-of-the-art rad-hard processor.
|
8 |
Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and RoutingCannon, Matthew Joel 01 August 2019 (has links)
Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the circuit's netlist and how the circuit is placed and routed on the FPGA. TMR with repair showed a neutron cross-section improvement of 100x while the best mitigation technique proposed in this work showed an improvement of 700x.This work demonstrates both some causes behind single bit SEU failures for TMR circuits on FPGAs and mitigation techniques to address these failures. In addition to these findings, this work also shows that the majority of radiation failures in these circuits are caused by multiple cell upsets, laying the path for future work to further enhance the effectiveness of TMR on FPGAs.
|
Page generated in 0.0342 seconds