Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences.

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

Cette thèse porte sur les architectures d’émission pour des terminaux mobiles multi-radio fonctionnant dans la bande de fréquences, 800 MHz - 6 GHz. Avec l’évolution constante des systèmes de communication, les terminaux doivent fonctionner dans plusieurs bandes de fréquences et modes, correspondant à une grande diversité de normes. Le concept d’une architecture multi-radio unique est une évolution de celui de l’émetteur-récepteur multistandard, caractérisé par une mise en parallèle des circuits pour chaque standard. Il permet alors d’optimiser coût et consommation. L’objet de l’étude est de concevoir des architectures d’émission flexibles, à la fois en fréquence et en format de modulation, capables de générer les formes d’ondes de tous les standards en respectant pour chacun le niveau de puissance en sortie et assurant un bon rendement. Ce type d’architectures pourrait, dans l’avenir, être utilisé pour des applications de radio cognitive. L’amplificateur de puissance est l’élément critique dans les émetteurs. Le principe de fonctionnement des amplificateurs impose un compromis entre la linéarité et le rendement en puissance. L’utilisation des amplificateurs en classes commutées permet d’améliorer les performances en rendement mais nécessite de revoir complètement les architectures classiques d’émission. Dans ce contexte, plusieurs architectures qui transforment les signaux avant l’amplificateur et qui peuvent être utilisées pour la multi-radio ont été considérées. Trois, en particulier, ont été analysées et comparées ; à savoir : l’architecture polaire avec codeur d’enveloppe sigma-delta, l’architecture polaire avec codeur d’enveloppe par largeur d’impulsion et l’architecture cartésienne sigma-delta. La validation a été faite sur les signaux les plus critiques en matière de dynamique de puissance et de bande passante, que sont les signaux LTE et WiMAX mobile. En sortie de l’amplificateur, le filtrage d’émission joue un rôle décisif et plusieurs technologies de filtrage sont envisageables. Dans ce cadre, on s’est plus particulièrement intéressé à la technologie BAW (Bulk Acoustic Wave) et un banc de filtres multi-radio a été synthétisé. Cette thèse a donc permis de chiffrer les performances clés d’un émetteur multi-radio à haut rendement en analysant du traitement en bande de base jusqu’au filtrage d’antenne / This research deals with wireless multi-radio transmitter architectures operating in the frequency band of 800 MHz – 6GHz. As a consequence of the constant evolution in the communication systems, the mobile transmitters must be able to operate at different frequency bands and modes according to existing standards specifications. The concept of a unique multi-radio architecture is an evolution of the multi-standard transceiver characterized by a parallelization of circuits for each standard. Multi-radio concept optimizes surface and power consumption. This study concentrates on flexible multi-radio architectures. This kind of architectures could be used in the future for cognitive radio applications. The power amplifier (PA) is the key element in transmitter architectures. Its operating principle establishes a trade-off between power efficiency and linearity. The utilization of a switched mode amplifier allows improving efficiency performances but implies a review of the classical transmitter architectures. Within this context, some architectures transforming the input signal of the PA and that are candidates for multi-radio applications are considered. In particular, three architectures have been analyzed and compared: the polar architecture with sigma-delta envelope modulator, the polar architecture with pulse width modulator and the cartesian sigma delta architecture. Validation is accomplished with the most critical signals in terms of power dynamics and frequency bandwidth; these are the LTE and mobile WiMAX. At the amplifier output, the band-pass filter plays a key role and many filtering technologies could be envisaged. In particular, we are interested in the BAW technology (Bulk Acoustic Wave) and a filter bank has been synthesized. This research has quantified the key performances of a high efficiency multi-radio transmitter by analyzing the system from baseband signal treatment to RF filtering before the antenna

Yes / New multi-standard wide band filters with compact sizes are designed for wireless communication devices. The proposed structures realize dual-wideband and quad-wideband characteristics by using a new skew-symmetrical coupled pair of asymmetric stepped impedance resonators, combined with other structures. The first and second dual-wideband filters realize fractional bandwidths (FBW) of 43.2%/31.9% at the central frequencies (CF) of 1.875/1.63 GHz, and second bandwidths of 580 MHz/1.75 GHz at CF of 5.52/4.46 GHz, respectively. The proposed quad-band filter realizes its first/second/third/fourth pass bands at CF 2.13/5.25/7.685/9.31 GHz with FBW of 46.0%/11.4%/4.6%and 5.4%, respectively. The wide pass bands are attributed to the mutual coupling of the modified ASIR resonators and their bandwidths are controllable by tuning relative parameters while the wide stop band performance is optimized by the novel interdigital cross coupled line structure and parallel uncoupled microstrip line structure. Moreover, the quad band is generated by introducing the novel defected rectangle structure. These multi-standard filters are simulated, fabricated and measured, and measured results agree well with both simulated results and theory predictions. The good in-band and out-of-band performances, the miniaturized sizes and simple structures of the proposed filters make them very promising for applications in future multi-standard wireless communication. / Horizon 2020 Framework Programme(European Union), Grant/Award Number:H2020-MSCA-ITN-2016 SECRET-722 424

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

La Radio Logicielle (SDR : Software Defined Radio) et la Radio Cognitive (CR : Cognitive Radio) deviennent d'un usage courant car elles répondent à plusieurs enjeux technico-économiques majeurs dans le domaine des télécommunications. Ces systèmes radio permettent de combler l'écart de développement technologique qui existe entre la partie matérielle et la partie logicielle des systèmes de communication, en permettant la gestion optimale des bandes de fréquences sous-utilisées par la commutation en temps réel d'une configuration radio à une autre. Dans ce cadre, cette thèse présente la mise en œuvre d'une chaîne de traitements Radio Logicielle (appelée SDR waveform) dans un Système Multiprocesseurs sur Puce (MPSoC) à usage général (implémenté dans un FPGA de type Xilinx Virtex-4). Cette plateforme est basée autour d'un Réseau sur Puce (NoC) interconnectant 16 processeurs élémentaires (appelés PE) disposant de quatre blocs-mémoires externes DDR2. Nous avons proposé des implémentations temps réel et embarquées sur MPSoC de différentes briques de traitements d'une chaîne SDR, en concevant une stratégie efficace de parallélisation et de synchronisation pour chaque composante élémentaire de la « waveform ». Nous avons amélioré la fonctionnalité de la chaîne de traitement Radio Logicielle, en intégrant un Transceiver reconfigurable basé sur différents modèles de Réseaux de Neurones Artificiels (RNA) : les Cartes Auto-Organisatrices (SOM), les Réseaux de Neurones Compétitifs (LVQ) et enfin les Réseaux Multi-Couches de Perceptrons (MLP). Ces trois RNA permettent la reconnaissance de la norme spécifique basée sur les paramètres d'entrée extraits du signal et la reconfiguration du Transceiver de CR. La solution adaptative que nous avons proposée commute vers le RNA le plus approprié en fonction des caractéristiques du signal d'entrée détecté. Il est important de pouvoir prendre en compte des signaux complexes et multi-porteuses. Dans ce cadre, nous avons adressé le cas d'un signal complexe composé de plusieurs porteuses, ainsi en divisant les PEs en différents groupes indépendants, nous affectons chaque groupe de PEs au traitement d'une nouvelle porteuse. Nous avons conçu une stratégie efficace de synchronisation et de parallélisation de ces trois RNA pour CR Transceiver. Nous l'avons appliquée, par la suite pour l'implantation de nos algorithmes sur le MPSoC déjà cité. L'accélération que nous obtenons pour la SDR waveform et pour les algorithmes de Transceiver de CR démontre que les MPSoC à usage général sont une réponse pertinente, entre autres, aux contraintes de performances sur une telle plateforme. Le système que nous proposons apporte une réponse aux défis technico-économiques des grandes entreprises qui investissent ou prévoient d'investir dans des équipements basés sur des SDR ou des CR, puisqu'il permet d'éviter de recourir à des équipements d'accélération coûteux. Nous avons, par la suite, ajouté d'autres fonctionnalités à notre waveform avec un « CR Transceiver multinormes », en proposant une nouvelle approche pour la gestion du spectre radio. Ceci étant l'aspect le plus important de CR. Nous rendons ainsi notre waveform spectralement efficace en modélisant les caractéristiques radiofréquences (RF) du signal utilisateur primaire sous la forme d'une série temporelle multi-variée. Cette série temporelle est ensuite fournie comme entrée dans un Réseau de Neurones Récurrent d'Elman (ERNN) qui prédit l'évolution de la série temporelle de RF pour déterminer si l'utilisateur secondaire peut exploiter la bande de fréquences. Nous avons exploité la cyclo-stationnarité inhérente des signaux primaires pour la Modélisation Non-Linéaire Autorégressive Exogène (NARX : Non-linear AutoRegressive Exogenous) des séries temporelles des caractéristiques RF, car la prédiction d'une caractéristique RF demande d'abord de connaître les autres caractéristiques radios pertinentes. Nous avons observé une tendance similaire pour les valeurs prédites et observées. En résumé, nous avons proposé des algorithmes pour SDR waveform à efficacité spectrale avec un Transceiver Universel, ainsi que leurs implantations parallèles sur MPSoC. Notre conception de waveform répond aux exigences en performances et aux contraintes de ressources embarquées des applications dans le domaine / Software Defined Radio (SDR) and Cognitive Radio (CR) are entering mainstream. These high performance and high adaptability requiring devices with agile frequency operations hold promise to :1. address the inconsistency between hardware and software advancements, 2. real time mode switching from one radio configuration to another and3. efficient spectrum management in under-utilized spectrum bands. Framed within this statement, in this thesis we have implemented a SDR waveform on 16 Processing Element (PE) Network on chip (NoC) based general purpose Multiprocessors System on chip (MPSoC), with access to four external DDR2 memory banks, which is implemented on a single chip Xilinx Virtex-4 FPGA. We shifted short term development of a waveform into software domain by designing an efficient parallelization and synchronization strategy for each waveform component, individually. We enhance our designed waveform functionality by proposing and implementing three Artificial Neural Networks Schemes : Self Organizing Maps, Linear Vector Quantization and Multi-Layer Perceptrons as effective techniques for reconfiguring CR Transceiver after recognizing the specific standard based on input parameters, pertaining to different layers, extracted from the signal. Our proposed adaptive solution switches to appropriate Artificial Neural Network, based on the features of input signal sensed. We designed an efficient synchronization and parallelization strategy to implement the Artificial Neural Networks based CR Transceiver Algorithms on the aforementioned MPSoC chip. The speed up we obtained for our SDR waveform and CR Transceiver algorithms demonstrated that the general purpose MPSoC devices are the most efficient answer to the acquisition challenge for major organizations that invest or plan to invest in SDR and CR based devices, thereby allowing us to avoid expensive hardware accelerators. We address the case of a complex signal composed of many modulated carriers by dividing the PEs in individual groups, thus received signal with more than one Standard is processed efficiently. We add further functionality in our designed Multi-standard CR Transceiver possessing SDR Waveform by proposing a new approach for radio spectrum management, perhaps the most important aspect of CR. We make our designed waveform Spectrum efficient by modelling the primary user signal Radio Frequency features as a multivariate time series, which is then given as input to Elman Recurrent Neural Network that predicts the evolution of Radio Frequency Time Series to decide if the secondary user can exploit the Spectrum band. We exploit the inherent cyclostationary in primary signals for Non-linear Autoregressive Exogenous Time Series Modeling of Radio Frequency features, as predicting one RF feature needs the previous knowledge of other relevant RF features. We observe a similar trend between predicted and actual values. Ensemble, our designed Spectrum Efficient SDR waveform with a Universal Multi-standard Transceiver answers the SDR and CR performance requirements under resource constraints by efficient algorithm design and implementation using lateral thinking that seeks a greater cross-domain interaction

Les travaux présentés dans la thèse portent sur la conception d'amplificateurs de puissance reconfigurables dans la technologie SiGe BiCMOS7RF de STMicroelectronics. Les applications visées sont les terminaux multi-standards de communications mobiles GSM/DCS/UMTS. Ces amplificateurs doivent être capables de modifier dynamiquement leurs propriétés en fonction à la fois du standard utilisé à un moment donné et du niveau de la puissance d'entrée afin de travailler à rendement optimum et préserver les batteries des terminaux. Pour cela, nous avons du faire face aux principaux points de divergence de ces standards: le rendement pour le GSM et le DCS afin de diminuer la puissance consommée et la linéarité pour l'UMTS qui utilise une modulation à enveloppe non-constante. L'amplificateur de puissance reconfigurable doit donc faire face à cette contradiction. Nous proposons une architecture capable d'adapter ses caractéristiques en fonction du standard choisi, en décrivant des méthodes permettant de modifier les caractéristiques principales de l'amplificateur : la classe de fonctionnement, le point de compression à 1 dB et le gain de la structure, le but étant de travailler à rendement optimum. Tous ces points de contrôles sont autant de leviers qui permettent de modifier les paramètres de l'amplificateur et de privilégier les critères de linéarité et de rendement l'un par rapport à l'autre, afin que l'amplificateur réponde aux spécifications du standard utilisé à un moment donné. La réalisation d'un amplificateur de puissance reconfigurable nous a permis de valider la fonctionnalité de la technique proposée. Mots-clés : multi-standard, circuits RF BiCMOS, amplificateur de puissance reconfigurable, classes de fonctionnement, variation du CP1, compromis linéarité-rendement, rendement optimum.

The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply.

The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless communication market. Although CMOS technology can provide most building blocks in RF transceivers, the implementation of CMOS RF power amplifiers is still a challenging task. The objective of this research is to develop design techniques to implement fully-integrated multi-mode power amplifiers using CMOS technology. In this dissertation, a load modulation technique with tunable matching networks and a pre-distortion technique in a multi-stage PA are proposed to support multi-communication standards with a single PA. A fully-integrated dual-mode GSM/EDGE PA was designed and implemented in a 0.18 um CMOS technology to achieve high output power for the GSM application and high linearity for the EDGE application. With the suggested power amplifier design techniques, fully-integrated PAs have been successfully demonstrated in GSM and EDGE applications. In Addition to the proposed techniques, a body-switched cascode PA core is also proposed to utilize a single PA in multi-mode applications without hurting the performance. With the proposed techniques, a fully-integrated multi-mode PA has been implemented in a 0.18 um CMOS technology, and the power amplifier has been demonstrated successfully for GSM/EDGE/WCDMA applications. In conclusion, the research in this dissertation provides CMOS RF power amplifier solutions for multiple standards in mobile wireless communications with low cost and high integration.

Software Defined Radio (SDR) and Cognitive Radio (CR) are entering mainstream. These high performance and high adaptability requiring devices with agile frequency operations hold promise to :1. address the inconsistency between hardware and software advancements, 2. real time mode switching from one radio configuration to another and3. efficient spectrum management in under-utilized spectrum bands. Framed within this statement, in this thesis we have implemented a SDR waveform on 16 Processing Element (PE) Network on chip (NoC) based general purpose Multiprocessors System on chip (MPSoC), with access to four external DDR2 memory banks, which is implemented on a single chip Xilinx Virtex-4 FPGA. We shifted short term development of a waveform into software domain by designing an efficient parallelization and synchronization strategy for each waveform component, individually. We enhance our designed waveform functionality by proposing and implementing three Artificial Neural Networks Schemes : Self Organizing Maps, Linear Vector Quantization and Multi-Layer Perceptrons as effective techniques for reconfiguring CR Transceiver after recognizing the specific standard based on input parameters, pertaining to different layers, extracted from the signal. Our proposed adaptive solution switches to appropriate Artificial Neural Network, based on the features of input signal sensed. We designed an efficient synchronization and parallelization strategy to implement the Artificial Neural Networks based CR Transceiver Algorithms on the aforementioned MPSoC chip. The speed up we obtained for our SDR waveform and CR Transceiver algorithms demonstrated that the general purpose MPSoC devices are the most efficient answer to the acquisition challenge for major organizations that invest or plan to invest in SDR and CR based devices, thereby allowing us to avoid expensive hardware accelerators. We address the case of a complex signal composed of many modulated carriers by dividing the PEs in individual groups, thus received signal with more than one Standard is processed efficiently. We add further functionality in our designed Multi-standard CR Transceiver possessing SDR Waveform by proposing a new approach for radio spectrum management, perhaps the most important aspect of CR. We make our designed waveform Spectrum efficient by modelling the primary user signal Radio Frequency features as a multivariate time series, which is then given as input to Elman Recurrent Neural Network that predicts the evolution of Radio Frequency Time Series to decide if the secondary user can exploit the Spectrum band. We exploit the inherent cyclostationary in primary signals for Non-linear Autoregressive Exogenous Time Series Modeling of Radio Frequency features, as predicting one RF feature needs the previous knowledge of other relevant RF features. We observe a similar trend between predicted and actual values. Ensemble, our designed Spectrum Efficient SDR waveform with a Universal Multi-standard Transceiver answers the SDR and CR performance requirements under resource constraints by efficient algorithm design and implementation using lateral thinking that seeks a greater cross-domain interaction