The objectives of this work are to review, investigate and model the microwave planar filters of the modern wireless communication system. The recent main stream of microwave filters are classified and discussed separately. Various microwave filters with detailed applications are investigated in terms of their geometrical structures and operational performances. A comprehensive theoretical study of microwave filters is presented. The main types of microwave filters including the basic low-pass filters such as Butterworth and Chebyshev filters are fully analysed and described in detail. The transformation from low-pass prototype filters to high-pass filters, band-pass filters and band-stop filters are illustrated and introduced. Research work on stepped impedance resonator (SIR) and asymmetric stepped impedance resonator (ASIR) structure is presented. The characteristics of λg/4, λg/2 and λg (λg is the guided wavelength of the fundamental frequency in the free space) type SIR resonators, and the characteristic of asymmetric SIR resonator are categorized and investigated. Based on the content mentioned above, novel multi-standard high performance asymmetric stepped impedance resonator single-wideband and dual-wideband filters with wide stopbands are proposed. The methodologies to realize wide passband and wide stop-band filters are detailed. In addition, multi-standard high performance triplewideband, quadruple-wideband and quint-wideband filters are suggested and studied. The measurement results for all prototype filters agree well with the theoretical predictions and simulated results from Ansoft HFSS software. The featured broad bandwidths over single/multiple applicable frequency bands and the high performances of the proposed filters make them very promising for applications in future multistandard wireless communication.

In video transmission there is a need to compose a wide-band signal from a numberof narrow-band sub-signals. A flexible solution offers the possibility to place any narrow-band sub-signal anywhere in the wide-band signal, making better use of the frequency space of the wide-band signal. A multi-standard supportive solution will also consider the three standard bandwidths of digital and analog video transmissions, both terrestrial and cable (6; 7 and 8 MHz), in use today. This thesis work will study the efficiency of a flexible aggregation solution, in terms of computational complexity and error vector magnitude (EVM). The solution uses oversampled complex modulated filter banks and inner channelizers, to reduce the total workload on the system. Each sub-signal is channelized through an analysis filter bank and together all channelized sub-signals are aggregated through one synthesis filter bank to form the wide-band composite signal. The EVM between transmitted and received sub-signals are investigated for an increasing number of sub-signals. The solution in this thesis work is performing good for the tested number of up to 100 narrow-band sub-signals. The result indicates that the multi-standard flexible aggregation solution is efficient for an increasing number of transmitted sub-signals.

Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given. / <p>QC 20140114</p>

The objectives of this work are to review, investigate and model the microwave planar filters of the modern wireless communication system. The recent main stream of microwave filters are classified and discussed separately. Various microwave filters with detailed applications are investigated in terms of their geometrical structures and operational performances. A comprehensive theoretical study of microwave filters is presented. The main types of microwave filters including the basic low-pass filters such as Butterworth and Chebyshev filters are fully analysed and described in detail. The transformation from low-pass prototype filters to high-pass filters, band-pass filters and band-stop filters are illustrated and introduced. Research work on stepped impedance resonator (SIR) and asymmetric stepped impedance resonator (ASIR) structure is presented. The characteristics of λg/4, λg/2 and λg (λg is the guided wavelength of the fundamental frequency in the free space) type SIR resonators, and the characteristic of asymmetric SIR resonator are categorized and investigated. Based on the content mentioned above, novel multi-standard high performance asymmetric stepped impedance resonator single-wideband and dual-wideband filters with wide stopbands are proposed. The methodologies to realize wide passband and wide stop-band filters are detailed. In addition, multi-standard high performance triplewideband, quadruple-wideband and quint-wideband filters are suggested and studied. The measurement results for all prototype filters agree well with the theoretical predictions and simulated results from Ansoft HFSS software. The featured broad bandwidths over single/multiple applicable frequency bands and the high performances of the proposed filters make them very promising for applications in future multistandard wireless communication.

Les émetteurs-récepteurs actuels tendent à devenir multi-standards c’est-àdireque plusieurs standards de communication peuvent cohabiter sur la même puce. Lespuces sont donc amenées à traiter des signaux de formes très différentes, et les composantsanalogiques subissent des contraintes de conception de plus en plus fortes associées au supportdes différentes normes. Les auto-interférences, c’est à dire les interférences généréespar le système lui-même, sont donc de plus en plus présentes, et de plus en plus problématiquesdans les architectures actuelles. Ces travaux s’inscrivent dans le paradigmede la « radio sale » qui consiste à accepter une pollution partielle du signal d’intérêtet à réaliser, par l’intermédiaire d’algorithmes, une atténuation de l’impact de ces pollutionsauto-générées. Dans ce manuscrit, on s’intéresse à différentes auto-interférences(phénomène de "spurs", de "Tx leakage", ...) dont on étudie les modèles numériques etpour lesquelles nous proposons des stratégies de compensation. Les algorithmes proposéssont des algorithmes de traitement du signal adaptatif qui peuvent être vus comme des« algorithmes de soustraction de bruit » basés sur des références plus ou moins précises.Nous dérivons analytiquement les performances transitionnelles et asymptotiques théoriquesdes algorithmes proposés. On se propose également d’ajouter à nos systèmes unesur-couche originale qui permet d’accélérer la convergence, tout en maintenant des performancesasymptotiques prédictibles et paramétrables. Nous validons enfin notre approchesur une puce dédiée aux communications cellulaires ainsi que sur une plateforme de radiologicielle. / Radio frequency transceivers are now massively multi-standards, which meansthat several communication standards can cohabit in the same environment. As a consequence,analog components have to face critical design constraints to match the differentstandards requirements and self-interferences that are directly introduced by the architectureitself are more and more present and detrimental. This work exploits the dirty RFparadigm : we accept the signal to be polluted by self-interferences and we develop digitalsignal processing algorithms to mitigate those aforementioned pollutions and improve signalquality. We study here different self-interferences and propose baseband models anddigital adaptive algorithms for which we derive closed form formulae of both transientand asymptotic performance. We also propose an original adaptive step-size overlay toimprove transient performance of our method. We finally validate our approach on a systemon chip dedicated to cellular communications and on a software defined radio.

Les émetteurs-récepteurs actuels tendent à devenir multi-standards c’est-àdireque plusieurs standards de communication peuvent cohabiter sur la même puce. Lespuces sont donc amenées à traiter des signaux de formes très différentes, et les composantsanalogiques subissent des contraintes de conception de plus en plus fortes associées au supportdes différentes normes. Les auto-interférences, c’est à dire les interférences généréespar le système lui-même, sont donc de plus en plus présentes, et de plus en plus problématiquesdans les architectures actuelles. Ces travaux s’inscrivent dans le paradigmede la « radio sale » qui consiste à accepter une pollution partielle du signal d’intérêtet à réaliser, par l’intermédiaire d’algorithmes, une atténuation de l’impact de ces pollutionsauto-générées. Dans ce manuscrit, on s’intéresse à différentes auto-interférences(phénomène de "spurs", de "Tx leakage", ...) dont on étudie les modèles numériques etpour lesquelles nous proposons des stratégies de compensation. Les algorithmes proposéssont des algorithmes de traitement du signal adaptatif qui peuvent être vus comme des« algorithmes de soustraction de bruit » basés sur des références plus ou moins précises.Nous dérivons analytiquement les performances transitionnelles et asymptotiques théoriquesdes algorithmes proposés. On se propose également d’ajouter à nos systèmes unesur-couche originale qui permet d’accélérer la convergence, tout en maintenant des performancesasymptotiques prédictibles et paramétrables. Nous validons enfin notre approchesur une puce dédiée aux communications cellulaires ainsi que sur une plateforme de radiologicielle. / Radio frequency transceivers are now massively multi-standards, which meansthat several communication standards can cohabit in the same environment. As a consequence,analog components have to face critical design constraints to match the differentstandards requirements and self-interferences that are directly introduced by the architectureitself are more and more present and detrimental. This work exploits the dirty RFparadigm : we accept the signal to be polluted by self-interferences and we develop digitalsignal processing algorithms to mitigate those aforementioned pollutions and improve signalquality. We study here different self-interferences and propose baseband models anddigital adaptive algorithms for which we derive closed form formulae of both transientand asymptotic performance. We also propose an original adaptive step-size overlay toimprove transient performance of our method. We finally validate our approach on a systemon chip dedicated to cellular communications and on a software defined radio.

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.