[pt] Neste trabalho apresenta-se uma metodologia pelo método dos elementos finitos para a análise estática-dinâmica bi-dimensional de linhas marítimas considerando-se o contato com o leito marinho. Para o cabo considera-se o elemento de dois nós do modelo de viga de Euler-Bernoulli com as grandezas estáticas e dinâmicas referidas a um sistema co- rotacionado. Considera-se a nãolinearidade geométrica associada ao movimento de corpo rígido da estrutura, supondo pequenas deformações. No movimento da linha, são consideradas as influências do peso próprio, empuxo, carregamentos hidrodinâmicos das correntes marinhas, deslocamentos prescritos no ponto superior da linha, forças de inercia e ação de flutuadores. Os efeitos sobre a linha associados ao contato com o fundo marinho são considerados empregando-se a técnica dos multiplicadores de Lagrange. Estes representam o carregamento (forças e momentos) requerido para garantir as restrições geométricas. No modelo não são considerados os efeitos das forças de atrito com o fundo marinho, cuja rigidez é considerada muito superior à do cabo. A matriz de rigidez usual do modelo de vigas é aumentada de forma a acomodar as novas incógnitas resultantes da imposição das condições de contato. Desta forma, condições de contato, separação repetidos (contato variável) e grandes movimentos relativos do cabo com o leito são contemplados pelo modelo. A solução das equações algébricas não-lineares, resultantes da integração temporal passo-a-passo de Newmark, é obtida com a técnica iterativa de Newton Raphson. A metodologia numérica foi implementada e resultados de alguns testes para situações da engenharia offshore são mostrados e comparados com os apresentados por outros autores independentes. / [en] In this work a finite element methodology for two- dimensional static and/or dynamic analysis of maritime risers including contact with the seabed is considered. The line is modeled by a two node beam element based on the Euler- Bernoulli theory with a co-rotational coordinate system, defined from the structure space coordinate nodes, to refer the element equilibrium and motion equations. Geometric non-linear effects are considered, all associated with rigid body motions from the structure, under small strain hypothesis. In the riser motion, the influences of its own weight, buoyancy forces, hydrodynamic loadings due to the maritime currents, the prescribed displacements at the top point line, the inertia forces and the floating action are considered. Effects on the line associated to the seabed contact are considered using Lagrange multipliers. They represent, the required loading (forces and moments) to ensure the cable geometric restrictions. In the model, friction forces effects on the seabed are not considered and the seabed stiffness is taken much greater than the riser s. The beam model stiffness matrix results into an increased matrix to accommodate the new model unknowns reactions, which are represented by the contact forces and moments. Similarly, conditions for variable contact and/or separation, as well as large relative motions between the flexible line and the seabed, are contemplated by the model. Solutions of the resulting nonlinear motion equations are obtained using Newmark s step-by-step time integration procedure with the Newton-Raphson iterative technique, for the numerical solution convergence. The methodology has been implemented and some representative offshore engineering testing analysis results are presented compared to other independently published solutions.

<p>Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem. </p><p>The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.</p>

<p>A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application.</p><p>These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area.</p><p>The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction.</p><p>The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.</p>

In digital communication systems, satellites give us world wide services. These satellites should effectively use the available bounded frequency spectrum and, therefore, to carry out flexible frequency-band reallocation (FFBR), on-board signal processing implementation on FFBR network is needed. In the future, to design desired dynamic communication systems, very flexible digital signal processing structures will be needed. The hardware, in the system, shall not be changed as simple changes in the software will be made. The purpose of this thesis is to implement an N-channel FFBR network, where N=20. A 20-channel FFBR network consists of different blocks, e.g., DFT, IDFT, complex multipliers, input/output commutators and polyphase components. The whole 20-channel FFBR network will be implemented in VHDL. In a 20-channel FFBR network, it is a 20-point FFT/IFFT required. This 20-point FFT/IFFT is built by a combination of radix-4 and radix-5 butterflies. The Cooley-Tukey FFT algorithm is chosen to build the 20-point FFT/IFFT. The main aim is to build 20-point FFT/IFFT. There are 20 complex multipliers before the IFFT block and 20 complex multipliers after the IFFT block. In the same way, 20 complex multipliers are used before the FFT block and 20 complex multipliers are used after the FFT block. At the input/output to this FFBR network, 20 FIR filters (polyphase components) are used, respectively.

Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem. The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.

The effective dose equivalent, H (or the effective dose, E ) to an individual is the primary limiting quantity in radiation protection. However, techniques for measuring H for neutrons have not been fully developed. In this regard a new tissue equivalent proportional counter (TEPC) based on a gas electron multiplier (GEM) for measuring H*(10), which is a conservative estimate of H, for neutrons was designed and constructed. The deposited energy distribution for two different neutron sources (a Cf-252 source and a AmBe source) was measured using the new TEPC. The measurements were performed using two different proportional gases: P-10 gas and a propane-based tissue equivalent gas at various pressures. A computer simulation of the new TEPC, based on the Monte Carlo method, was performed in order to obtain the pulse height distributions for the two neutron sources. The simulated results and the measured results were compared. Results show that the experimental results agree with the computational results within 20% of accuracy for both Cf-252 and AmBe neutron sources. A new model GEM-based TEPC was developed for use in obtaining H*(10). The value of H*(10) for the Cf-252 source and for the AmBe source using experimental measurements was obtained. These results are presented in this study. The study shows that the GEM-based TEPC can successfully estimate H*(10). With these results and some refinements, this GEM-based TEPC can directly be used as a neutron rem meter.

This research study focuses on providing evidence that indicates that, making use of contemporary green building practices within a low cost subsidised housing project have more social, economical as well as environmental benefits than that of a conventional, non-green approach. Low cost subsidised housing units have become an everyday sight in the light of the global as well as the local economy. The increasing levels of unemployment and subsequent social problems lead to growing needs for this form of housing. As these projects consume a number of resources, steps need be taken to lighten the load – such as the carbon emissions - that is put on the environment. According to the United Nations, the key areas that are influenced by sustainability are environmental, economical as well as social. In South Africa, a number of government as well as local policies exist that regulates the planning and building practices of the low cost subsidised housing projects. These policies have been used as a foundation for this study. This study focuses on the Lufhereng project as a case study, and technology used in the Kuyasa as well as Cosmo City developments furthermore assisted in the groundwork for the comparison between the different construction approaches. The challenges facing the utilisation of a contemporary green building approach were researched, identified, discussed and recommendations were made. SAM (social accounting matrix) multiplier analysis on the Gauteng SAM obtained from the DBSA (Development Bank of South Africa), analysis and comparison of existing data as well as a qualitative questionnaire that was sent to industry stakeholders were utilised to obtain relevant information. The quantitative as well as qualitative data obtained from the primary as well as secondary research indicated that there are a number of aspects which has an influence on method of construction used in subsidised low cost housing units. The findings from literature as well as empirical research were analysed and discussed accordingly. Recommendations and suggestions regarding strategies that may be followed to increase the use of contemporary green approaches in these projects were made. These recommendations were based on the findings from literature as well as the research conducted for this study. The use of contemporary green approaches are vital for the social, economic as well as environmental sustainability of the country, and thus, ultimately of the world as a whole. It is, in this light, imperative that everything in our power should be done to preserve our resources by any means possible. / PhD (Urban and Regional Planning), North-West University, Potchefstroom Campus, 2013

This research study focuses on providing evidence that indicates that, making use of contemporary green building practices within a low cost subsidised housing project have more social, economical as well as environmental benefits than that of a conventional, non-green approach. Low cost subsidised housing units have become an everyday sight in the light of the global as well as the local economy. The increasing levels of unemployment and subsequent social problems lead to growing needs for this form of housing. As these projects consume a number of resources, steps need be taken to lighten the load – such as the carbon emissions - that is put on the environment. According to the United Nations, the key areas that are influenced by sustainability are environmental, economical as well as social. In South Africa, a number of government as well as local policies exist that regulates the planning and building practices of the low cost subsidised housing projects. These policies have been used as a foundation for this study. This study focuses on the Lufhereng project as a case study, and technology used in the Kuyasa as well as Cosmo City developments furthermore assisted in the groundwork for the comparison between the different construction approaches. The challenges facing the utilisation of a contemporary green building approach were researched, identified, discussed and recommendations were made. SAM (social accounting matrix) multiplier analysis on the Gauteng SAM obtained from the DBSA (Development Bank of South Africa), analysis and comparison of existing data as well as a qualitative questionnaire that was sent to industry stakeholders were utilised to obtain relevant information. The quantitative as well as qualitative data obtained from the primary as well as secondary research indicated that there are a number of aspects which has an influence on method of construction used in subsidised low cost housing units. The findings from literature as well as empirical research were analysed and discussed accordingly. Recommendations and suggestions regarding strategies that may be followed to increase the use of contemporary green approaches in these projects were made. These recommendations were based on the findings from literature as well as the research conducted for this study. The use of contemporary green approaches are vital for the social, economic as well as environmental sustainability of the country, and thus, ultimately of the world as a whole. It is, in this light, imperative that everything in our power should be done to preserve our resources by any means possible. / PhD (Urban and Regional Planning), North-West University, Potchefstroom Campus, 2013

Local procurement by public bodies is one type of Short Food Supply Chain (SFSC), which have been argued to contribute to economic regeneration and local sustainable development. In the current UK policy environment, quantifying actual local economic gains could add much-needed weight to arguments in favour of local procurement in the NHS and other public bodies. To aid such quantification, this paper exemplifies and evaluates the use of a ¿quick and simple¿ tool called LM3, designed to measure the local economic benefit of initiatives like SFSCs. LM3 is calculated for the Cornwall Food Programme (CPF), a localised procurement initiative. The findings confirm that the CPF has a considerable impact on the local economy. Notwithstanding this conclusion, difficulties in data collection combined with inaccuracies inherent to the LM3 process created a large margin of error in the findings. Moreover, a qualitative evaluation of the CPF added a valuable understanding of the wider economic impact of the CFP. The use of an even simpler and more reliable ¿LM2¿ multiplier tool is recommended for future studies, accompanied by some qualitative evaluation to create a fuller picture of local economic impacts.