The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever before. Symbiote Coprocessor Unit (SCU), developed by Dr. Pranav Vaidya, is a hardware accelerator which has potential of providing data processing speedup of up to 150x compared with traditional data stream processors. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvement. Mr. Tareq S. Alqaisi, an MSECE graduate from IUPUI worked on curbing these limitations. In his architecture, he used a Xilinx MicroBlaze microcontroller to reduce the complexity of SCU along with few other modifications. The objective of this study is to make SCU suitable for mass production while reducing its power consumption and delay. To accomplish this, the execution unit of SCU has been implemented in application specific integrated circuit and modules such as ACG/OCG, sequential comparator, and D-word multiplier/divider are integrated into the design. Furthermore, techniques such as operand isolation, buffer insertion, cell swapping, and cell resizing are also integrated into the system. As a result, the new design attains 67.9435 µW<p></p> of dynamic power as compared to 74.0012 µW<p></p> before power optimization along with a small increase in static power, 39.47 ns of clock period as opposed to 52.26 ns before time optimization.

Diese Diplomarbeit untersucht die Optimierung eines Mean-Variance Portfolios auf einem vollständigen Markt unter der Bedingung, dass die Insolvenz des Investors ausgeschlossen ist. Hierbei wird die duale Methode (auch Martingalmethode genannt)

In preparation for the High-Luminosity Large Hadron Collider (HL-LHC) at CERN, the Compact Muon Solenoid (CMS) Detector is undergoing a series of upgrades to its existing infrastructure, and is adding in several completely new subdetector systems. The first of these new systems, called GE1/1, is a series of 144 gas electron multiplier (GEM) detectors, arranged as 36 two-detector "superchambers" in each of the muon endcaps of CMS. These detectors are a subtype of micropattern gas detectors, and consist of three layers of "GEM foils", thin sheets of polyimide coated with 5 um of copper on each side and chemically etched with holes of 50 - 70 um diameter at a pitch of 140 um. These layers are stacked on top of a printed circuit board (PCB) readout and sealed within a gastight volume that is filled with Ar:CO2 70:30, and a high voltage is applied to the foils to create electric fields within the GEM detectors. When a muon enters the detector and ionizes the gas within, the ionized electrons encounter these fields and multiply in Townsend avalanches at each successive foil layer, until they are read out at the readout PCB at a gain of ~10^4. In early 2017, a demonstrator system known as the "slice test" was installed into the negative endcap. Consisting of 10 GEM detectors, the two-year-long slice test served as both a proof of concept for the GE1/1 system and an invaluable learning experience that would permanently impact not only the GE1/1 project, but future GEM systems GE2/1 and ME0 as well. During the slice test, it was observed that readout channels were being lost in the course of operation to such a degree that the operational lifetime of the system was in serious jeopardy. These losses were attributed to damage to the front-end readout ASIC (VFAT) inputs, caused propagating electrical discharges within the detectors, and a dedicated campaign to study the discharges was launched. The results of this study will be presented in this dissertation. A campaign to mitigate these discharges and their resulting damage was launched. In order to protect the sensitive VFAT from damage, several external protection circuits were proposed and thoroughly tested. The results of these tests, which are presented herein, determined that a series of resistors totaling 470 Ohms would be installed on the VFAT hybrid. When coupled with an additional 200 kOhm resistor on the HV filter, this reduced the probability of damage following a discharge from 93% to 3% As GE2/1 and ME0 are not due to be installed for another few years, more complex discharge-prevention measures can be put into place. As such, the following measures have been examined, and results will be discussed herein: A new, larger VFAT hybrid is being manufactured, whose larger surface area can accommodate more robust protection circuits than those considered and used for GE1/1. As well, double-segmented GEM foils, in which both the top and bottom of each foil is segmented into < 100 cm^2 sectors that are separated by resistors, were examined for use in the detectors. These double-segmented foils were found to introduce a cross-talk signal in the detectors that results in false signals being treated as true signals, which causes a saturation of the GEM bandwidth and results in unwanted dead time. These cross-talk signals, as well as the compromises made to reduce the cross-talk while maintaining robust discharge prevention, will be discussed. / Doctorat en Sciences / info:eu-repo/semantics/nonPublished

A team from Brigham Young University and I performed full-scale lateral load tests on individual and grouped 12.75x0.375 inch pipe piles spaced at varying distances behind an MSE wall. The individually loaded pile which acted as a control was spaced at 4.0 pile diameters from the wall face, and the three grouped piles which were loaded in unison were spaced at 3.0, 2.8, and 1.8 pile diameters from the wall face and transversely spaced at 4.7 pile diameters center-to-center. The purpose of these tests was to determine the extent of group effects on lateral pile resistance, induced loads in soil reinforcements, and MSE wall panel deflections compared to those previously observed in individually laterally loaded piles behind MSE walls. The computer model LPILE was used in my analysis of the measured test data. The p-multipliers back-calculated with LPILE for the grouped piles were 0.25, 0.60, and 0.25 for the grouped piles spaced at 3.0, 2.8, and 1.8 pile diameters from the wall, respectively. These values are lower than that predicted for piles at the same pile-to-wall spacings using the most recent equation for computing p-multipliers. I propose the use of an additional p-multiplier for grouped piles near an MSE wall, a group-effect p-multiplier, to account for discrepancies between individual and grouped pile behaviors. The group effect p-multipliers were 0.35, 0.91, and 0.74 for the grouped piles spaced at 3.0, 2.8, and 1.8 pile diameters from the wall, respectively. The average group-effect p-multiplier was 0.66. Additionally, I used LPILE to analyze test data from Pierson et al. (2009), who had previously performed full-scale lateral load tests of individual and grouped shafts. In said analysis, the group of three 3-foot diameter concrete shafts spaced at 2.0 shaft diameters from the wall face and transversely spaced at 5.0 shaft diameters center-to-center had an average group effect p-multiplier of 0.78. As in previous studies, the induced forces in soil reinforcements in this study were greatest either near the locations of the test piles or at the MSE wall face. The most recent equation for calculating the maximum induced force in a soil reinforcement strip was reasonably effective in predicting the measured maximum loads when superimposed between the test piles, with 65% and 85% of the data points falling within the one and two standard deviation boundaries, respectively, of the original data used to develop the equation. Deflection of the MSE wall panels was greater during the grouped pile test than was previously observed for individually loaded piles under similar pile head deflections--with a maximum wall deflection of 0.31 inch compared to the previous average of 0.10 inch for pile head deflections of about 1.25 inches.

Installing load bearing piles within the reinforcement zone of mechanically stabilized earth (MSE) retaining walls is common practice in the construction industry. Bridge abutments are often constructed in this manner to adapt to increasing right-of-way constraints, and must be capable of supporting horizontal loads imposed by, traffic, earthquakes, and thermal expansion and contraction. Previous researchers have concluded that lateral pile resistance is reduced when pile are placed next to MSE walls but no design codes have been established to address this issue. Full –scale testing of statically applied lateral loads to four 24”x0.5” pipe piles, and cyclically applied lateral load to four 12.75”x0.375” pipe piles placed 1.5-5.3 pile diameters behind a 20-foot MSE wall was performed. The MSE wall was constructed using 5’x10’ concrete panels and was supported with ribbed strip and welded wire streel reinforcements. The computer software LPILE was used to back-calculate P-multipliers for the 24” piles. P-multipliers are used to indicate the amount of reduction in lateral resistance the piles experience due to their placement near the MSE wall. Previous researchers have proposed that any pile spaced 3.9 pile diameters (D) or more away from the MSE wall will have a P-multiplier of 1; meaning the pile experiences no reduction in lateral resistance due to its proximity to the wall. P-multipliers for piles spaced closer than 3.9D away from the wall decrease linearly as distance from the wall decreases. P-multipliers for the 24” piles spaced 5.1D, 4.1D, 3.0D, and 2.0D were 1, 0.84, 0.55, and 0.44 respectively. Lateral resistance of the 12.75” cyclically loaded piles decreased as the number of loading cycles increased. Lateral resistance of the piles when loads were applied in the direction of the wall was less than the lateral resistance of the piles when loads were applied away from the wall at larger pile head loads. The maximum tensile force experienced by the soil reinforcements generally occurred near the wall side of the pile face when the lateral loads were applied in the direction of the wall. Behind the pile, the tensile force decreased as the distance from the wall increased. Equation 5-4, modified from Rollins (2018) was found to be adequate for predicting the maximum tensile force experienced by the ribbed strip reinforcements during the static loading of the 24” pipe piles, particularly for lower loads. About 65% of the measured forces measured in this study fell within the one standard deviation boundary of the proposed equation.

<p>Modern massive data, with enormous sample size and tremendous dimensionality, are usually stored and processed using a cluster of nodes in a master-worker architecture. A shortcoming of this architecture is that inter-node communication can be over a thousand times slower than intra-node computation, which makes communication efficiency a desirable feature when developing distributed learning algorithms. In this dissertation, we tackle this challenge and propose communication-efficient bootstrap methods for simultaneous inference in the distributed computational framework.</p> <p>  </p> <p>First, we propose two generic distributed bootstrap methods, \texttt{k-grad} and \texttt{n+k-1-grad}, which apply multiplier bootstrap at the master node on the gradients communicated across nodes. Based on them, we develop a communication-efficient method of producing an $\ell_\infty$-norm confidence region using distributed data with dimensionality not exceeding the local sample size. Our theory establishes the communication efficiency by providing a lower bound on the number of communication rounds $\tau_{\min}$ that warrants the statistical accuracy and efficiency and showing that $\tau_{\min}$ only increases logarithmically with the number of workers and the dimensionality. Our simulation studies validate our theory.</p> <p>  </p> <p>Then, we extend \texttt{k-grad} and \texttt{n+k-1-grad} to the high-dimensional regime and propose a distributed bootstrap method for simultaneous inference on high-dimensional distributed data. The method produces an $\ell_\infty$-norm confidence region based on a communication-efficient de-biased lasso, and we propose an efficient cross-validation approach to tune the method at every iteration. We theoretically prove a lower bound on the number of communication rounds $\tau_{\min}$ that warrants the statistical accuracy and efficiency. Furthermore, $\tau_{\min}$ only increases logarithmically with the number of workers and the intrinsic dimensionality, while nearly invariant to the nominal dimensionality. We test our theory by extensive simulation studies and a variable screening task on a semi-synthetic dataset based on the US Airline On-Time Performance dataset.</p>

Pólya and Schur completely characterized all real-rootedness preserving linear operators acting on the standard monomial basis in their famous work from 1914. The corresponding eigenvalues are from then on known as multiplier sequences. In 2009 Borcea and Br\"and\'en gave a complete characterization for general linear operators preserving real-rootedness (and stability) via the symbol. Relying heavily on these results, in this thesis, we are able to completely characterize multiplier sequences for generalized Laguerre bases. We also apply our methods to reprove the characterization of Hermite multiplier sequences achieved by Piotrowski in 2007.

Indiana University-Purdue University Indianapolis (IUPUI) / The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever before. Symbiote Coprocessor Unit (SCU), developed by Dr. Pranav Vaidya, is a hardware accelerator which has potential of providing data processing speedup of up to 150x compared with traditional data stream processors. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvement. Mr. Tareq S. Alqaisi, an MSECE graduate from IUPUI worked on curbing these limitations. In his architecture, he used a Xilinx MicroBlaze microcontroller to reduce the complexity of SCU along with few other modifications. The objective of this study is to make SCU suitable for mass production while reducing its power consumption and delay. To accomplish this, the execution unit of SCU has been implemented in application specific integrated circuit and modules such as ACG/OCG, sequential comparator, and D-word multiplier/divider are integrated into the design. Furthermore, techniques such as operand isolation, buffer insertion, cell swapping, and cell resizing are also integrated into the system. As a result, the new design attains 67.9435 µW of dynamic power as compared to 74.0012 µW before power optimization along with a small increase in static power, 39.47 ns of clock period as opposed to 52.26 ns before time optimization.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第20033号 / 情博第628号 / 新制||情||109(附属図書館) / 33129 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 髙木 直史, 教授 小野寺 秀俊, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

京都大学 / 0048 / 新制・論文博士 / 博士(理学) / 乙第13201号 / 論理博第1560号 / 新制||理||1635(附属図書館) / 京都大学大学院理学研究科数学・数理解析専攻 / (主査)教授 宍倉 光広, 教授 泉 正己, 教授 國府 寛司 / 学位規則第4条第2項該当 / Doctor of Science / Kyoto University / DFAM