The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management aspects of communication synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core interface redesign, requires the development of a Core-Network Interface (CNI) which allows them to communicate over the on-chip network. The absence of intelligence amongst the NoC components, entails the introduction of a CNI capable of not only providing basic packetization and depacketization, but also other essential services such as reliability, power management, reconguration and test support. A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation. Rising on-chip communication power costs and reliability concerns due to these, motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations. A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated. Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques. Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con- dence in the correct operation of on-chip cores. The rising design complexity and IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line scheme capable of managing IP core test in the presence of executing applications is essential. Such a scheme ensures application performance and system power budgets are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT) for NoC-based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct operation of the SoC.

Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at the intermediate nodes between source and destination. In this work, we propose a novel router microarchitecture which offers superior performance versus typical synchroniz- ing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26 percent at low loads and increases saturation throughput by up to 50 percent.

This thesis aims to design a Network-on-Chip (NoC) that performs wormhole flow control method and source routing and aims to describe the design in VHDL language and implement it on an FPGA platform. In order to satisfy the diverse needs of different network traffic, the thesis aims to design the NoC in such a way that it can be modified via a user interface, which changes the descriptions in the VHDL source code. Network topology, number of router ports, number of virtual channels, buffer size and flit size are the features of the designed NoC that can be modified. In this thesis, interfaces and operations of the blocks in the NoC are defined through block diagrams and algorithmic state machines. Verification of these blocks is performed not only on computer environment via simulations tools, but also in real world. To achieve this, source nodes generating dummy flits are also designed which communicate with our user interface via RS-232 generating flits according to the information provided by the user and monitoring the received flits from other source nodes in real-time.

The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management aspects of communication synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core interface redesign, requires the development of a Core-Network Interface (CNI) which allows them to communicate over the on-chip network. The absence of intelligence amongst the NoC components, entails the introduction of a CNI capable of not only providing basic packetization and depacketization, but also other essential services such as reliability, power management, reconguration and test support. A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation. Rising on-chip communication power costs and reliability concerns due to these, motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations. A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated. Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques. Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con- dence in the correct operation of on-chip cores. The rising design complexity and IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line scheme capable of managing IP core test in the presence of executing applications is essential. Such a scheme ensures application performance and system power budgets are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT) for NoC-based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct operation of the SoC.

In chip-multiprocessor (CMP) designs, when the number of core increases, the size of on-chip communication fabric and data storage grows accordingly and therefore the chip power challenge is exacerbated. This thesis work considers the power management for networks-on-chip (NoC) and the last level cache, which constitute the uncore in CMP designs. NoC is regarded as a scalable approach to cope with the increasing demand for on-chip communication bandwidth. The last level cache is shared among all cores. The focus of this work is on the control techniques for uncore dynamic voltage and frequency scaling. A realistic but not well-studied scenario is investigated. That is, the entire uncore shares a single voltage/frequency domain, as opposed to separated domains in most of previous works. One appealing advantage here is that data packets no longer experience the interfacing overhead across different voltage/frequency domains. The classic PI (Proportional and Integral) control method is adopted due to its simplicity, flexibility and low implementation overhead. This thesis research outcome includes three parts. First, stability of the PI control is analyzed. Second, a model-assisted PI control scheme is proposed and studied. The model assist is to address the problem that no universally good reference point exists for the control. Third, the windup issue for the PI control is investigated. Full architecture simulations are performed on public benchmark suites to validate the proposed techniques. The result show 76% energy reduction with less than 6% performance degradation compared to constantly high voltage/frequency for uncore.

With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication paradigm to solve this by using highly scalable and efficient packet switched network. The addition of intelligent networking on the chip adds to the chip’s power consumption thus making management of communication power an interesting and challenging research problem. While VLSI techniques have evolved over time to enable power reduction in the circuit level, the highly dynamic nature of modern large SoC demand more than that. This dissertation explores some innovative dynamic solutions to manage the ever increasing communication power in the post sub-micron era. Today’s highly integrated SoCs require great level of cross layer optimizations to provide maximum efficiency. This dissertation aims at the dynamic power management problem from top. Starting with a system level distribution and management down to microarchitecture enhancements were found necessary to deliver maximum power efficiency. A distributed power budget sharing technique is proposed. To efficiently satisfy the established power budget, a novel flow control and throttling technique is proposed. Finally power efficiency of underlying microarchitecture is explored and novel buffer and link management techniques are developed. All of the proposed techniques yield improvement in power-performance efficiency of the NoC infrastructure.

Les densités d'intégration actuelles des circuits intégrés permettent de disposer de SoC (systèmes sur puce) de plus en plus complexes, intégrant de plus en plus de standards. Par conséquent, le problème des interconnexions entre tous les blocs IP (Intellectual Property) constituant le SoC devient un point critique que les structures de communications actuelles ne parviennent plus à solutionner.<br />Ces problèmes sont notamment liés aux besoins de plus en plus forts en mobilité et en débit dans les architectures de communication actuelles et futures. Ainsi, les solutions à base de NoC (Network on Chip) offrent de bonnes perspectives en terme de bande passante et de flexibilité pour pallier notamment aux limites actuelles des topologies bus. Les travaux de thèse présentés ici portent sur la méthodologie de modélisation et d'exploration d'architectures de réseaux sur puce appliquée aux télécommunications.<br />Le contexte radio-télécommunications étudié est celui proposé dans le cadre du projet Européen 4MORE pour lequel nous avons contribué. Une des contraintes de ce projet était d'intégrer dans un SoC la technique MC-CDMA (Multiple Carrier Code Division Multiple Access) combinant la technique MIMO en utilisant un média de communication innovant.<br />Ainsi, nous avons contribué à cette intégration en proposant une méthodologie de conception permettant d'aider le concepteur dans le choix des différents paramètres caractérisant le NoC pour satisfaire les contraintes temps réel de l'application spécifiées dans le cahier des charges.<br />Ces travaux de thèse ont porté sur la modélisation et l'interconnexion des composants IP constituant la chaîne algorithmique du projet 4MORE afin de les intégrer dans un modèle SystemC du NoC. Par ailleurs, les choix de dimensionnement du réseau et des contraintes de placement des blocs IP sur celui-ci ont un impact important sur les performances globales de l'application. Nous avons mis en place un outil AAA (Adéquation Algorithme Architecture) permettant de réaliser l'adéquation des contraintes de l'application sur l'architecture en minimisant les chemins de communication tout en veillant à ne pas violer les bandes passantes théoriques des liens de communication entre routeurs.<br />Le flot de conception mis en œuvre permet au concepteur de générer le modèle SystemC du NoC et permettra à cours terme de générer le code VHDL associé du modèle SystemC simulé afin d'accélérer les phases de simulation et de donner la possibilité de valider logiciellement et matériellement (cible FPGA) l'architecture avec son application.

Continuous semiconductor technology scaling and the rapid increase in computational needs have stimulated the emergence of multi-/many-core processors. While up to hundreds of cores can be placed on a single chip, the performance capacity of the cores cannot be fully exploited due to high latencies of interconnects and memory, high power consumption, and low manufacturing yield in traditional (2D) chips. 3D stacking is an emerging technology that aims to overcome these limitations of 2D designs by stacking processor dies over each other and using through-silicon-vias (TSVs) for on-chip communication, and thus, provides a large amount of on-chip resources and shortens communication latency. These benefits, however, are limited by challenges in high power densities and temperatures. 3D stacking also enables integrating heterogeneous technologies into a single chip. One example of heterogeneous integration is building many-core systems with silicon-photonic network-on-chip (PNoC), which reduces on-chip communication latency significantly and provides higher bandwidth compared to electrical links. However, silicon-photonic links are vulnerable to on-chip thermal and process variations. These variations can be countered by actively tuning the temperatures of optical devices through micro-heaters, but at the cost of substantial power overhead. This thesis claims that unearthing the energy efficiency potential of 3D-stacked systems requires intelligent and application-aware resource management. Specifically, the thesis improves energy efficiency of 3D-stacked systems via three major components of computing systems: cache, memory, and on-chip communication. We analyze characteristics of workloads in computation, memory usage, and communication, and present techniques that leverage these characteristics for energy-efficient computing. This thesis introduces 3D cache resource pooling, a cache design that allows for flexible heterogeneity in cache configuration across a 3D-stacked system and improves cache utilization and system energy efficiency. We also demonstrate the impact of resource pooling on a real prototype 3D system with scratchpad memory. At the main memory level, we claim that utilizing heterogeneous memory modules and memory object level management significantly helps with energy efficiency. This thesis proposes a memory management scheme at a finer granularity: memory object level, and a page allocation policy to leverage the heterogeneity of available memory modules and cater to the diverse memory requirements of workloads. On the on-chip communication side, we introduce an approach to limit the power overhead of PNoC in (3D) many-core systems through cross-layer thermal management. Our proposed thermally-aware workload allocation policies coupled with an adaptive thermal tuning policy minimize the required thermal tuning power for PNoC, and in this way, help broader integration of PNoC. The thesis also introduces techniques in placement and floorplanning of optical devices to reduce optical loss and, thus, laser source power consumption. / 2018-03-09T00:00:00Z

Les progrès dans le domaine des semi-conducteurs ont permis la miniaturisation des puces et l’extension considérable de leurs capacités de calcul et de mémorisation. Cela s’est accompagné d’un accroissement très important du volume des données échangées à l’intérieur de ces puces, limitant les performances au débit de données dans la puce. Ainsi, les concepteurs ont proposé le réseau sur puce (ou NoC : Network-on-Chip) afin de répondre à ces besoins. Cependant, l’accroissement du trafic permis par ce réseau se traduit par une consommation énergétique plus importante engendrant une hausse de la température et une diminution de la fiabilité de la puce. L’élaboration de techniques d’optimisation de l’énergie du NoC est alors nécessaire. La première partie de cette thèse est consacrée à l’étude de la modélisation des NoCs afin d’estimer leur consommation et d’identifier les composants les plus consommateurs. Ainsi, la première contribution de cette thèse a été d’améliorer la modélisation du NoC en modifiant le modèle d’interconnexions d’un simulateur de NoC existant (Noxim), pour le rendre bit-près (Noxim-XT), et ainsi permettre au simulateur d’incorporer un modèle d’interconnexions considérant les effets du crosstalk, phénomène physique faisant varier leur consommation d’énergie. La seconde partie de la thèse traite de l’optimisation de la consommation d’énergie du NoC. Ainsi, la recherche d’optimisation s’est orientée vers la réduction d’énergie des liens étant donné leur importante contribution énergétique dans la consommation d’énergie dynamique du réseau. De plus, la part de l’énergie dynamique tend à augmenter avec l’évolution de la technologie. Nous avons proposé à l’issue de cette étude deux techniques d’optimisation pour les interconnexions du NoC. Ces deux optimisations proposent des compromis énergie / latence différents et une extension possible de ces travaux pourrait être la mise en oeuvre de la sélection de l’optimisation selon les besoins de l’application en cours. / Thanks to the technology’s shrinking, a considerable amount of memory and computing capacity can be embedded into a single chip. This improvement leads to an important increase of the bandwidth requirements, that becomes the bottleneck of chip performances in terms of computational power. Thus, designers proposed the Network-on-Chip (NoC) as an answer to this bandwidth challenge. However, the on-chip traffic growth allowed by the NoC causes a significant rise of the chip energy consumption, which leads to a temperature increase and a reliability reduction of the chip. The development of energy optimization techniques for NoC becomes necessary.The first part of this thesis is devoted to the study of NoCs power models in order to estimate accurately the consumption of each component. Then, we can identify which ones are the most power consuming. Hence, the first contribution of this thesis has been to improve the NoC power model by replacing the lilnk power model in a NoC simulator (Noxim) by a bit-accurate one (Noxim-XT). In this way, the simulator is able to consider Crosstalk effects, a physical phenomenon that increases links energy consumption. The second part of the thesis deals with NoC energy optimization techniques. Thus, our research of optimization techniques is focused on inter-router links since their energy contribution regarding the NoC dynamic energy is significant and the dynamic energy tends to stay prominent with the shrinking technology. We proposed two optimization techniques from the study of NoC links optimizations. These two techniques present different energy / latency compromises and a possible extension of this work could be the development of a transmission strategy in order to select the right technique according to the application requirements.

The technology push by Moore's law brings a paradigm shift in the adaption of many core systems which replace high frequency superscalar processors with many simpler ones. On the software side, in order to utilize the available computational power, applications are following the high performance parallel/multi-threading model. Thus, many-core systems raise the challenges of resource allocation and fragmentation making necessary ecient run-time resource management techniques. In this thesis, we propose SPA, a Simple Pool Architecture for managing resource allocation in many-core systems. The proposed framework follows a distributed approach in which cores are organized into clusters and multiple clusters form a pool. Clusters are created based on system's characteristics and the allocation of cores is performed in a distributed manner so as to increase resource utilization and reduce fragmentation. Specifically, SPA is responsible (i) to generate the pool-based structure and organize cores into clusters depending on the NoC architecture; (ii) to serve, at run-time, the needs of multithreaded applications, in terms or processing cores; and (iii) to allocate resources in order to take advantage of spatial features, shared resources and reduce fragmentation. Experimental results show that SPA produces on average 15% better application response time while waiting time is reduced by 45% on average compared to other state-of-art methodologies.