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Cette thèse porte principalement sur la caractérisation électrique et la modélisation physique d'éléments mémoires émergents de type OxRRAM (Oxide Resistive Random Access Memory) intégrant soit un oxyde de nickel, soit un oxyde de hafnium. Une fois la maturité technologique atteinte, ce concept de mémoire est susceptible de remplacer la technologie Flash qui fait encore figure de référence. Les principaux avantages de la technologie OxRRAM reposent sur une très bonne compatibilité avec les filières CMOS, un faible nombre d'étapes de fabrication, une grande densité d'intégration et des performances attractives en termes de fonctionnement. Le premier objectif de ce travail concerne le diélectrique employé dans les cellules. Il s'agit d'apporter des éléments factuels permettant d'orienter un choix technologique sur la méthode d'élaboration de l'oxyde de nickel (oxydation thermique ou pulvérisation cathodique réactive) puis d'évaluer les performances de cellules à base d'oyxde de hafnium. Le second objectif est d'approfondir la compréhension des mécanismes physiques responsables du changement de résistance des dispositifs mémoire par une approche de modélisation physique des phénomènes opérant lors des phases d'écriture et d'effacement, sujet encore largement débattu dans la communauté scientifique. Le troisième objectif de cette thèse est d'évaluer, par le biais de caractérisations électriques, les phénomènes parasites intervenant dans les éléments mémoires de type 1R (élément résistif sans dispositif d'adressage) et, en particulier, la décharge capacitive apparaissant lors de leur programmation (opérations d'écriture). / This work is focused on the electrical characterization and physical modeling of emerging OxRRAM memories (Oxide Resistive Random Access Memory) integrating nickel or hafnium oxide. After reaching maturity, this memory concept is likely to replace the Flash technology which is still a standard in the CMOS industry. The main advantages of resistive memories technology is their good compatibility with CMOS processes, a small number of manufacturing steps, a high integration density and their attractive performances in terms of memory operation. The first objective of this thesis is to provide enough informations allowing to orientate the elaboration process of the active nickel oxide layer (thermal oxidation, reactive sputtering) then to compare the performances of the fabricated cells with devices featuring a hafnium oxide layer. The second objective is to understand the physical mechanisms responsible of the device resistance change. A physical model is proposed allowing to apprehend SET and RESET phenomenon in memory devices, subject which is still widely debated in the scientific community. The third objective of this thesis is to evaluate electrical parasitic phenomenon observed in 1R-type memory elements (resistive element without addressing device), in particular the parasitic capacitance appearing during cell programming (writing operation).

Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-07-03T15:03:25Z No. of bitstreams: 1 TES_TACIANO_DRECKMANN_PEREZ_COMPLETO.pdf: 1779781 bytes, checksum: 2111ccea963be0eea76bdbb7d24321d9 (MD5) / Made available in DSpace on 2017-07-03T15:03:25Z (GMT). No. of bitstreams: 1 TES_TACIANO_DRECKMANN_PEREZ_COMPLETO.pdf: 1779781 bytes, checksum: 2111ccea963be0eea76bdbb7d24321d9 (MD5) Previous issue date: 2017-05-03 / Sistemas computacionais da atualidade tradicionalmente separam mem?ria e armazenamento. Linguagens de programa??o tipicamente refletem essa distin??o usando diferentes representa??es para dados em mem?ria (ex. estruturas de dados, objetos) e armazenamento (ex. arquivos, bancos de dados). A movimenta??o de dados entre esses dois n?veis e representa??es, bidirecionalmente, compromete tanto a efici?ncia do programador quanto de execu??o dos programas. Tecnologias recentes de memoria n?o-vol?til, tais como mem?ria de transi??o de fase, resistiva e magnetoresistiva, possibilitam combinar mem?ria principal e armazenamento em uma ?nica entidade de mem?ria persistente, abrindo caminho para abstra??es mais eficientes para lidar com persist?ncia de dados. Essa tese de doutorado introduz uma abordagem de projeto para o ambiente de execu??o de linguagens com ger?ncia autom?tica de mem?ria, baseado numa combina??o original de persist?ncia ortogonal, programa??o para mem?ria persistente, persist?ncia por alcance, e transa??es com atomicidade em caso de falha. Esta abordagem pode melhorar significativamente a produtividade do programador e a efici?ncia de execu??o dos programas, uma vez que estruturas de dados em mem?ria passam a ser persistentes de forma transparente, sem a necessidade de programar explicitamente o armazenamento, e removendo a necessidade de cruzar fronteiras sem?nticas. De forma a validar e demonstrar a abordagem proposta, esse trabalho tamb?m apresenta JaphaVM, a primeira M?quina Virtual Java especificamente projetada para mem?ria persistente. Resultados experimentais usando benchmarks e aplica??es reais demonstram que a JaphaVM, na maioria dos casos, executa as mesmas opera??es cerca de uma a duas ordens de magnitude mais rapidamente do que implementa??es equivalentes usando bancos de dados ou arquivos, e, ao mesmo tempo, requer significativamente menos linhas de c?digo. / Current computer systems separate main memory from storage. Programming languages typically reflect this distinction using different representations for data in memory (e.g. data structures, objects) and storage (e.g. files, databases). Moving data back and forth between these different layers and representations compromise both programming and execution efficiency. Recent nonvolatile memory technologies, such as Phase-Change Memory, Resistive RAM, and Magnetoresistive RAM make it possible to collapse main memory and storage into a single layer of persistent memory, opening the way for simpler and more efficient programming abstractions for handling persistence. This Ph.D. thesis introduces a design for the runtime environment for languages with automatic memory management, based on an original combination of orthogonal persistence, persistent memory programming, persistence by reachability, and lock-based failure-atomic transactions. Such design can significantly increase programming and execution efficiency, as in-memory data structures are transparently persistent, without the need for programmatic persistence handling, and removing the need for crossing semantic boundaries. In order to validate and demonstrate the proposed concepts, this work also presents JaphaVM, the first Java Virtual Machine specifically designed for persistent memory. In experimental results using benchmarks and real-world applications, JaphaVM in most cases executed the same operations between one and two orders of magnitude faster than database- and file-based implementations, while requiring significantly less lines of code.

La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontrée. / The component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Nanokristalle werden beispielsweise für eine Anwendung in Solarzellen, Lichtemittern und nichtflüchtigen Datenspeichern diskutiert. Damit diese Anwendungen funktionieren können, ist eine genaue Kontrolle der Kristallitgröße sowie der Flächendichte und Lage der Kristallite in der Matrix wichtig. Zudem sollte die Matrix amorph sein, da amorphe Matrixmaterialien die Nanokristall-Oberfläche besser passivieren und beständiger gegen Leckströme sind. In dieser Arbeit werden Ge-Nanokristalle in die Hoch-Epsilon-Dielektrika ZrO2 und TaZrOx eingebettet. Im System Ge/ZrO2 kristallisieren die Ge-Cluster und die ZrO2-Matrix bei der gleichen Temperatur. Aufgrund der kristallinen Matrix weicht die Form der Ge-Nanokristalle von einer Kugel ab, worunter unter anderem die Größenkontrolle leidet. Die Beimischung von Ta2O5 stabilisiert die amorphe Phase des ZrO2 und verhindert dadurch die gemeinsame Kristallisation. Dadurch wird es im System Ge/TaZrOx möglich, kugelförmige Ge-Nanokristalle im Größenbereich von 3 nm bis 6 nm positionskontrolliert in eine amorphe Matrix einzubetten. Für die Untersuchung einer möglichen Anwendung des Materialsystems wurden Speicherzellen eines nichtflüchtigen Datenspeichers auf Basis von Ge-Nanokristallen hergestellt. Dabei zeigte sich, dass das System Ge/TaZrOx überdurchschnittlich viele Ladungen speichert und daher für diese Anwendung vielversprechend ist. Zudem stabilisiert die Beimischung von Ta2O5 eine extrem seltene orthorhombische Modifikation des ZrO2. Für ferroelektrische Datenspeicher könnte diese Phase eine aussichtsreiche Alternative zum HfO2 sein.

No description available.

In an era in which the amount of produced and stored data continues to exponentially grow, standard memory concepts start showing size, power consumption and costs limitation which make the search for alternative device concepts essential. Within a context where new technologies such as DRAM, magnetic RAM, resistive RAM, phase change memories and eFlash are explored and optimized, ferroelectric memory devices like FeRAM seem to showcase a whole range of properties which could satisfy market needs, offering the possibility of creating a non-volatile RAM. In fact, hafnia and zirconia-based ferroelectric materials opened up a new scenario in the memory technology scene, overcoming the dimension scaling limitations and the integration difficulties presented by their predecessors perovskite ferroelectrics. In particular, HfₓZr₁₋ₓO₂ stands out because of high processing flexibility and ease of integration in the standard semiconductor industry process flows for CMOS fabrication. Nonetheless, further understanding is necessary in order tocorrelate device performance and reliability to the establishment of ferroelectricity itself. The aim of this work is to investigate how the composition of the ferroelectric oxide, together with the one of the electrode materials influence the behavior of a ferroelectric RAM. With this goal, different process parameters and reliability properties are considered and an analysis of the polarization reversal is performed. Starting from undoped hafnia and zirconia and subsequently examining their intermixed system, it is shown how surface/volume energy contributions, mechanical stress and oxygen-related defects all concur in the formation of the ferroelectric phase. Based on the process optimization of an HfₓZr₁₋ₓO₂-based capacitor performed within these pages, a 64 kbit 1T1C FeRAM array is demonstrated by Sony Semiconductor Solutions Corporation which shows write voltage and latency as low as 2.0 V and 16 ns, respectively. Outstanding retention and endurance performances are also predicted, which make the addressed device an extremely strong competitor in the semiconductor scene.

Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013