The storage hardware is evolving at a rapid pace to keep up with the exponential rise of data consumption. Recently, ultra-fast storage technologies such as nano-second scale byte- addressable Non-Volatile Memory (NVM), micro-second scale SSDs are being commercialized. However, the OS storage stack has not been evolving fast enough to keep up with these new ultra-fast storage hardware. Hence, the latency due user-kernel context switch caused by system calls and hardware interrupts is no longer negligible as presumed in the era of slower high latency hard disks. Further, the OS storage stack is not designed with multi-core scalability in mind; so with CPU core count continuously increasing, the OS storage stack particularly the Virtual Filesystem (VFS) and filesystem layer are increasingly becoming a scalability bottleneck. Applications bypass the kernel (kernel-bypass storage stack) completely to eliminate the storage stack from becoming a performance and scalability bottleneck. But this comes at the cost of programmability, isolation, safety, and reliability. Moreover, scalability bottlenecks in the filesystem can not be addressed by simply moving the filesystem to the userspace. Overall, while designing a kernel-bypass storage stack looks obvious and promising there are several critical challenges in the aspects of programmability, performance, scalability, safety, and reliability that needs to be addressed to bypass the traditional OS storage stack. This thesis proposes a series of kernel-bypass storage techniques designed particularly for fast memory-centric storage. First, this thesis proposes a scalable persistent transactional memory (PTM) programming model to address the programmability and multi-core scalability challenges. Next, this thesis proposes techniques to make the PTM memory safe and fault tolerant. Further, this thesis also proposes a kernel-bypass programming framework to port legacy DRAM-based in-memory database applications to run on persistent memory-centric storage. Finally, this thesis explores an application-driven approach to address the CPU side and storage side bottlenecks in the deep learning model training by proposing a kernel-bypass programming framework to move to compute closer to the storage. Overall, the techniques proposed in this thesis will be a strong foundation for the applications to adopt and exploit the emerging ultra-fast storage technologies without being bottlenecked by the traditional OS storage stack. / Doctor of Philosophy / The storage hardware is evolving at a rapid pace to keep up with the exponential rise of data consumption. Recently, ultra-fast storage technologies such as nano-second scale byte- addressable Non-Volatile Memory (NVM), micro-second scale SSDs are being commercialized. The Operating System (OS) has been the gateway for the applications to access and manage the storage hardware. Unfortunately, the OS storage stack that is designed with slower storage technologies (e.g., hard disk drives) becomes a performance, scalability, and programmability bottleneck for the emerging ultra-fast storage technologies. This has created a large gap between the storage hardware advancements and the system software support for such emerging storage technologies. Consequently, applications are constrained by the limitations of the OS storage stack when they intend to explore these emerging storage technologies. In this thesis, we propose a series of novel kernel-bypass storage stack designs to address the performance, scalability, and programmability limitations of the conventional OS storage stack. The kernel-bypass storage stack proposed in this thesis is carefully designed with ultra-fast modern storage hardware in mind. Application developers can leverage the kernel-bypass techniques proposed in this thesis to develop new applications or port the legacy applications to use the emerging ultra-fast storage technologies without being constrained by the limitations of the conventional OS storage stack.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2017-12-11T16:00:35Z No. of bitstreams: 1 Gianlucca_Oliveira_Puglia_dis.pdf: 2043630 bytes, checksum: f7fc70f33d1d15b56eded8458fbed2fa (MD5) / Approved for entry into archive by Tatiana Lopes (tatiana.lopes@pucrs.br) on 2017-12-18T11:25:26Z (GMT) No. of bitstreams: 1 Gianlucca_Oliveira_Puglia_dis.pdf: 2043630 bytes, checksum: f7fc70f33d1d15b56eded8458fbed2fa (MD5) / Made available in DSpace on 2017-12-18T11:49:55Z (GMT). No. of bitstreams: 1 Gianlucca_Oliveira_Puglia_dis.pdf: 2043630 bytes, checksum: f7fc70f33d1d15b56eded8458fbed2fa (MD5) Previous issue date: 2017-03-21 / As tecnologias de mem?rias n?o-vol?teis s?o uma grande promessa na ?rea de arquitetura de computadores e ? esperado que sejam poderosas ferramentas para solucionar os problemas referentes a manipula??o eficiente de dados dos dias de hoje. Estas tecnologias prov?m alta performance e acesso em granularidade de bytes com a distinta vantagem de serem persistentes. Por?m, afim de explorar estas tecnologias em todo seu potencial, os sistemas e arquiteturas de hoje precisam buscar meios de se adaptar a esta nova forma de acessar dados e de superar os desafios que v?m com ela.Trabalhos existentes na ?rea j? prop?em m?todos para adaptar as arquiteturas existentes para o uso de NVM bem como formas inovadoras de empregar estas mem?rias em futuras aplica??es. No entanto, o suporte dos sistemas operacionais a estas solu??es, ainda que existente, ainda ? muito limitado. Neste trabalho, n?s apresentamos duas varia??es da chamada de sistema msync, modeladas para explorar as caracter?sticas das tecnologias de NVM e garantir consist?ncia para os dados dos usu?rios. Ambas s?o solu??es simples que permitem aos usu?rios definirem checkpoints de seus arquivos usando a sintaxe comum de sistemas de arquivos. N?s implementamos e testamos estes m?todos sobre o sistema operacional Linux utilizando como base um sistema de arquivo nativamente voltado a NVM. Nossos resultados mostram que estes mecanismos s?o capazes de garantir a integridade dos arquivos mesmo na presen?a de falhas no sistema enquanto mant?m uma performance razo?vel. / Upcoming non-volatile memory technologies are a big promise in computer architecture and are expected to be powerful tools to address today?s issues regarding efficient data manipulation. They provide high performance and byte granularity while also having the distinct advantage of being persistent. However in order to explore these technologies to their full potential, existing systems and architecture must adapt to this new way of working with data and workaround the challenges that come with it. Existing work in the area already proposes methods to adapt existing architecture to NVM as well as innovative ways to employ these memories in future applications. However operating system support to such NVM-enabled solutions, although existent, still very limited. In this work, we present two variations of the existing mmap system call, designed to both explore NVM characteristics and provide user data consistency. Both are very simple solutions that allow users to control the persistence and define checkpoints to their files while using the common mapped file syntax. We have implemented and tested these methods over Linux using a NVM file system as our base. Our results show that these mechanisms can ensure file integrity in the presence of system failures while also providing a reasonable performance.

Le regain d'attention des industriels pour les mémoires non volatiles intégrant des nanocristaux, illustré par l'introduction sur le marché de la Flexmemory de Freescale en technologie 90 nm, incite à poursuivre des études sur ce type de systèmes. Pour cela, nous avons mis au point des cellules mémoires élémentaires, à savoir des transistors MOS dont l'oxyde de grille contient une grille granulaire formée par un plan de nanocristaux de silicium (Si-ncx) stockant la charge électrique.Ce travail présente les principaux résultats issus de ces travaux, ceux-ci allant du procédé de fabrication à la caractérisation fine des dispositifs mémoires. Le parfait contrôle de l'élaboration de la grille granulaire de Si-ncx par implantation ionique à très basse énergie (ULE-IBS) est accompagné de caractéristiques « mémoires » répondant aux normes industrielles d'endurance et d'une discrimination des pièges responsables du chargement. Le stockage majoritaire par les Si-ncx est démontré, ce qui est essentiel pour la rétention de la charge. Nous avons développé une technique électrique permettant d'extraire à la fois la quantité de charge stockée par les Si-ncx mais également leurs principales caractéristiques structurales (taille, densité, position dans l'oxyde). Cette extension de la technique électrique de « pompage de charges », non destructive et in-situ permet de suivre l'état du composant en fonctionnement et de caractériser des pièges (e.g. les Si-ncx) pour la première fois au-delà de 3 nm de profondeur dans l'oxyde. Ces résultats ont été validés par des observations TEM. La résolution du pompage de charge étant le piège unique, nous avons alors couplé l'ULE-IBS avec la lithographie « Stencil » pour réduire latéralement le nombre de Si-ncx synthétisés. Cette technique nous permet pour le moment de contrôler la synthèse locale à la position désirée dans l'oxyde de « poches » de Si-ncx de 400 nm. La synthèse de « quelques » Si-ncx est envisagée à très court terme. Nous serons alors en mesure de fabriquer des mémoires à nombre choisi de nanocristaux (par SM-ULE-IBS), dont les propriétés structurales (taille, densité, position) et électriques (quantité de charge stockée) seront vérifiées par pompage de charge, offrant ainsi des outils puissants pour la fabrication et la caractérisation de mémoires à nombre réduit de nanocristaux, notamment pour des longueurs de grilles inférieures à 90 nm / The aim of this thesis has been to fabricate and electrically characterize elementary memory cells containing silicon nanocrystals (Si-ncs), in other words MOSFET which insulating layer (SiO2) contains a Si-ncs array storing the electrical charge. We have shown that we perfectly control the synthesis of a 2D array of 3-4 nm Si-ncs embedded into the MOSFET oxide by low-energy ion implantation (1-3 keV) Reaching this goal implied two key steps: on the one hand develop a reliable MOSFET fabrication process incorporating the Si-ncs synthesis steps and on the other hand develop tools and methods for both memory window and Si-ncs array itself characterizations. We have developed an in-situ characterization technique based on the well-known charge pumping technique, allowing for the first time the extraction of traps depth (e.g. the Si-ncs array) further than 3 nm into the oxide layer leading to the characterization of both position of these Si-ncs into the SiO2 matrix and their structural properties (diameter, density). These results have been confirmed by EF-TEM measurements. Finally, we have worked on the improvement of controlled local synthesis of Si-ncs pockets by combining low-energy ion implantation and stencil lithography. We reduced the size of these pockets down to about 400 nm using this parallel, low cost and reliable technique and identified the limiting effect for the pockets size reduction. These results pave the way for memory cells containing a few Si-ncs with a well-defined position into the oxide and a well-controlled number of ncs

Resistive random access memory (RRAM) is a non-volatile memory technology based on resistive switching in a dielectric or semiconductor sandwiched between two different metals. Also known as memristors, these devices are potential candidates for a next-generation replacement for flash memory. In this thesis, bipolar resistive switching is reported for the first time in solution-deposited zinc-tin-oxide (ZTO). The impact of the compliance current on device operation, including the SET and RESET voltages, pre-SET, RESET and post-RESET currents, the resistance ratio between the low and high resistance states, retention, and the endurance, is investigated for an isolated Al dot/ZTO/Ir blanket device and for Al/ZTO/Pt crossbar RRAM devices. A gradual forming process is devised to improve device stability and performance. It is found that the device performance depends critically on the compliance current density that is used to limit the breakdown conduction during the SET operation. In addition, it was found that the conduction and switching mechanisms are consistent with the filament model of formation and rupture of conductive filaments. / Graduation date: 2012

Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mémoire Flash conventionnelle. Les PCM offrent une grande variété de fonctions, comme une lecture et une écriture rapide, un excellent potentiel de miniaturisation, une compatibilité CMOS et des performances élevées de rétention de données à haute température et d'endurance, et peuvent donc ouvrir la voie à des applications non seulement pour les dispositifs mémoires, mais également pour les systèmes informatiques à hautes performances. Cependant, certains problèmes de fiabilité doivent encore être résolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mémoire Flash.Ce travail se concentre sur l'étude de mémoires à changement de phase intégrées afin d'optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications à hautes températures. Afin d'améliorer la fiabilité de la technologie, la stœchiométrie du matériau à changement de phase a été conçue de façon appropriée et des dopants ont été ajoutés, optimisant ainsi la stabilité thermique. Une diminution de la vitesse de programmation est également rapportée, ainsi qu'un drift résiduel de la résistance de l'état de faiblement résistif vers des valeurs de résistance plus élevées au cours du temps.Une nouvelle technique de programmation est introduite, permettant d'améliorer la vitesse de programmation des dispositifs et, dans le même temps, de réduire avec succès le phénomène de drift en résistance. Par ailleurs, un algorithme de programmation des PCM multi-bits est présenté. Un générateur d'impulsions fournissant des impulsions avec la tension souhaitée en sortie a été conçu et testé expérimentalement, répondant aux demandes de programmation d'une grande variété de matériaux innovants et en permettant la programmation précise et l’optimisation des performances des PCM. / Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology.

abstract: Deep neural networks (DNNs) have had tremendous success in a variety of statistical learning applications due to their vast expressive power. Most applications run DNNs on the cloud on parallelized architectures. There is a need for for efficient DNN inference on edge with low precision hardware and analog accelerators. To make trained models more robust for this setting, quantization and analog compute noise are modeled as weight space perturbations to DNNs and an information theoretic regularization scheme is used to penalize the KL-divergence between perturbed and unperturbed models. This regularizer has similarities to both natural gradient descent and knowledge distillation, but has the advantage of explicitly promoting the network to and a broader minimum that is robust to weight space perturbations. In addition to the proposed regularization, KL-divergence is directly minimized using knowledge distillation. Initial validation on FashionMNIST and CIFAR10 shows that the information theoretic regularizer and knowledge distillation outperform existing quantization schemes based on the straight through estimator or L2 constrained quantization. / Dissertation/Thesis / Masters Thesis Computer Engineering 2019

No description available.

Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon.

Les mémoires non-volatiles à grille flottante sont utilisées pour le stockage d'information sous la forme d'une charge électrique contenue dans la grille flottante d'un transistor. Le comportement de ces dispositifs mémoire est fortement lié aux propriétés de leur oxyde tunnel, qui permet à la fois le passage de cette charge lors d'opérations de programmation ainsi que sa rétention en l'absence d'alimentation électrique. Au cours de ce travail, des mesures de courant tunnel ont été réalisées sur des capacités semiconducteur-oxyde-semiconducteur de grande surface représentatives de la zone d'injection des cellules mémoire. L'application de pulses courts sur la grille de ces structures de test, au cours desquels le courant peut être mesuré en temps réel, a permis de mettre en évidence les principales propriétés transitoires et stationnaires pouvant affecter le fonctionnement des dispositifs mémoire. L'effet de la dégradation des oxydes tunnel, qui impacte le comportement des cellules mémoire lors des opérations de programmation et de la rétention, a été observé et interprété dans le cas d'un stress à tension constante. Les résultats obtenus sur les capacités de grande surface ont pu être utilisés dans le cadre d'une modélisation de cellules EEPROM. / Floating gate non-volatile memory devices are used to store data under the form of an electric charge contained in the floating gate of a transistor. The behavior of these memory devices is strongly linked to the properties of their tunnel oxide, which allows the transit of this charge during write/erase operations as well as its retention while the transistor is not polarized. During this work, tunneling current measurements have been performed on large area semiconductor-oxide-semiconductor capacitors that are representative of the injection zone of memory cells. The application of short pulses to the gates of these test structures, during which the current can be measured as a function of time, allowed the observation of the main transient and steady-state properties that can affect the functioning of memory devices, The effect of tunnel oxide degradation, which impacts the behavior of memory cells during write/erase operations as well as data retention, has been observed and interpreted in the case of a constant voltage stress. The results obtained on large area capacitors have been used to model EEPROM cells.

Android forensics has evolved over time offering significant opportunities and exciting challenges. On one hand, being an open source platform Android is giving developers the freedom to contribute to the rapid growth of the Android market whereas on the other hand Android users may not be aware of the security and privacy implications of installing these applications on their phones. Users may assume that a password-locked device protects their personal information, but applications may retain private information on devices, in ways that users might not anticipate. In this thesis we will be concentrating on one such application called 'WhatsApp', a popular social networking application. We will be forming an outline on how forensic investigators can extract useful information from WhatsApp and from similar applications installed on an Android platform. Our area of focus is extraction and analysis of application user data from non-volatile external storage and the volatile memory (RAM) of an Android device.