Esse trabalho teve como objetivo a produção e a caracterização elétrica de filmes finos de telureto com nanopartículas de ouro, depositados pela técnica sputtering, para aplicação em dispositivos de memória. Os filmes finos foram produzidos a partir de alvos cerâmicos de telureto (TeO2-ZnO) e foram nucleadas nanopartículas de ouro para observar sua influência no comportamento de memória. Foi desenvolvida metodologia adequada para a nucleação das nanopartículas por meio de tratamento térmico. Foram produzidos filmes com diferentes concentrações e tamanhos de nanopartículas e diferentes fluxos de oxigênio durante a deposição. Os filmes foram caracterizados por técnicas como Microscopia Eletrônica de Transmissão (TEM), Perfilometria, Espectrometria por Retroespalhamento de Rutherford (RBS) e extração de curvas de Corrente x Tensão (I-V). Por meio das medidas I-V foi possível identificar as melhores condições para aplicações em memória e correlacioná-las com as variáveis de processo estudadas. Resultados obtidos mostraram que a melhor condição para aplicações em memória não volátil foi encontrada em filmes com 100 nm de espessura e depositados com fluxo de oxigênio de 1 sccm, abertura do shutter em 50 e tratados termicamente por 10 ou 20 horas à 325 ºC. Nesses casos, foi observado um abrupto aumento na corrente (4 ordens de grandeza) em aproximadamente 6,5 V para 10 horas de tratamento térmico e 3,5 V para 20 horas de tratamento térmico, indicando a transição do estado inicial de baixa condutividade para outro de alta condutividade. As nanopartículas de ouro proporcionam maior capacidade de armazenamento de elétrons e não favorecem o transporte de corrente através do isolante; elas atuam como armadilhas para as cargas elétricas, o que reduz a corrente de fuga para níveis mais baixos. Foi estudada a influência do diâmetro e da concentração volumétrica das nanopartículas de ouro no valor da tensão elétrica associada à transição abrupta da corrente. Este parâmetro desempenha um papel importante no efeito de memória, pois determina a facilidade/dificuldade em se preencher e saturar as armadilhas (nanopartículas de ouro) com elétrons. Os materiais estudados neste trabalho mostraram-se promissores para aplicações em dispositivos de memória não volátil e possuem características semelhantes aos materiais orgânicos usados para o referido fim. / This work has the objective to fabricate and characterize electrically tellurite thin films containing gold nanoparticles, deposited by the sputtering technique, for application in memory devices. Thin films were produced from ceramic tellurite targets and gold nanoparticles were nucleated in order to observe their influence on memory behavior. An appropriate method was developed for the nucleation of the nanoparticles by means of heat treatment. Films with different nanoparticles sizes and concentration and different oxygen fluxes during the deposition, were produced. The films were characterized by techniques such as Transmission Electron Microscopy (TEM), Profilometry, Rutherford Backscatter Spectrometry (RBS) and current x voltage (I-V) curves. Using I-V measurements, it was possible to identify the best conditions for memory applications and correlate them with the process variables studied. The results showed that the best condition for memory applications was found in films with 100 nm thickness and deposited with oxygen flow of 1 sccm, opening shutter in 50 and heat treated for 10 or 20 hours at 325 ºC. In these cases, current abrupt increase (4 orders of magnitude) was observed at about 6.5 V for 10 hours of heat treatment and 3.5 V for 20 hours of heat treatment, indicating the transition from high impedance state to low impedance state. Gold nanoparticles provide a larger electron storage capability, and do not favor the electric transport through the insulator; they act as traps for electrical charges, which reduces the leak current to lower levels. It was studied the influence of the gold nanoparticles diameter and volumetric concentration on the voltage associated to the abrupt current. These parameters played an important role in the memory effect, as they determined the facility/difficulty to fill and saturate the traps (Au nanoparticles) with electrons. The materials studied in the present work, based on TeO2-ZnO thin films with Au nanoparticles, are promising for applications in nonvolatile memory device with similar characteristics to organic materials used for the same purpose.

Recently, memory-cells employing discrete traps as the charge storage media have been attracting a lot of attention as a promising candidate to replace conventional DRAM or Flash memories. Conventional floating gate (FG) non-volatile memories (NVMs) present critical issues on device scalability beyond the sub-50nm node. In achieving non-volatility in conventional FG memories, thicker control and tunnel oxide (~8nm) are required to guarantee longer retention time. Relatively, nano-dots memories causes more resistant leakage charges by localized storage sites, thus improving the device retention characteristics. Hence, nano-dots memories allow more aggressive scaling of the tunnel oxide and exhibit superior characteristics compared to Flash memories in term of operation voltage, write / erase speed, retention time and endurance. The advantages of metal nano-dots compared with other material counterparts include higher density of states , stronger coupling with the channel, better size scalability, and the design freedom of engineering the work function to optimize device characteristics. However, tungsten nano-dots are the most interested in all of metal dots is that tungsten metal has more extra attractive advantages, such as ultra high melting point make high process temperature caused superior thermal stability of device and wide application in VLSI technology nowadays caused real possibility of tungsten nano-dots NVMs fabricated in industry in practice. This dissertation is divided into four sections: (1) discussion of basic properties for tungsten nano-dots memory devices; (2) Tunneling Oxide Engineering,; (3) Improvement by novel processes; and (4) The influence with supercritical CO2 (SCCO2) and vapor treatment. Initially, formative mechanism of tungsten nano-dots and electrical characteristics of devices was investigated in the first section. Tungsten nano-dots were formed by oxidizing tungsten silicide / amorphous silicon double stack film at high temperature condition. From electrical measurement, the better characteristics have been achieved for oxidation condition at 1050¢XC / 120 sec. Secondly, the rapid thermal anneal (RTA) oxidation is used to grow tunnel oxide by two different forming gas (O2/N2O). Comparison of electrical characteristics, program characteristics of the device using tunnel oxide with N2O process is inferior than the common device. However, endurance is a important electrical characteristics in the semiconductor device especially apply on the non-volatile memory. Thirdly, novel processes were employed into fabrication of tungsten nano-dots memory devices, include the N2O oxidation and NH3 plasma treatment. The purpose of novel processes is production additional trapping states in nonvolatile memories, which is considerably as combination nano-dots with SONOS structure. In the final section, the application of supercritical CO2 with vapor on tungsten nano-dots memoery devices have been studying. It is found that the device treated by SCCO2 which electrical characteristics is improved obviously. Furthermore, this technology also can fabricate the nano-dots memory which is like the device used high temperature oxidation process. It suggests that the SCCO2 with vapor treatment could oxidize silicide film under a low temperature environment. This novel oxidation process has some advantages and could be noticed in the semiconductor industry.

Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.

Non-volatile memory can keep the data without supplying power, and it is suitable for portable electronic products due to the advantage of low power consumption. In current industrial production, high-temperature and long-time process are necessary for the fabrication of non-volatile memory, which are heavy loadings on production capacity and lots cost. Therefore, decreasing the temperature of the process is a trend. Recently using the oxidation treatment of supercritical carbon dioxide fluid can efficiently decrease the temperature of the process. In this thesis, the mixture layer of Zn, Sn, and SiO2 is applied to reduce the temperature of process, and to employ the defects of ZnO and SnO2 as floating gate for electron storage to fabricate the nonvolatile memory device. Zn and Sn are applied due to the low temperature melting points. To ensure the layer of cosputtering with Zn and Sn to be able to successfully fabricate as nano material device, the process of traditional rapid temperature annealing treatment was applied for first step. The co-sputtered Zn-Sn-SiO2 thin film was deposited on the tunneling oxide layer, and then the thin film was treated with varied annealing temperature to precipitate ZnO and SnO2 nanocrystals. After that, the C-V measurement is applied to analyze the change of the electrical and material properties. Using a positive bias, the electrons are injected into the oxide layer, by the threshold voltage the offset is occurred, which is defined as the memory window of the memory effect, and the property of nonvolatile memory will be applied. In addition, no matter the charge is injected from the gate oxide or tunnel oxide, the defects position of DLTS¡¦s peak is with the same property. The supercritical carbon dioxide fluid technology has been performed to study the memory effect. The capability of electron injection, storages and the defect, in the storage layer were studied by the C-V measurement and DLTS. The experiment confirmed that the Zn-Sn alloy has the memory property after it been treated by the supercritical carbon dioxide fluid technology. It has shown that Zn can promote to the storage capability ability due to the formation of deep level defects of SnO2 from the DLTS spectra. A new species is found at 0.93 eV with low activation energy and high capability of electron storage. The defect formation mechanism of Zn, ZnO, Zn-O-Si, Sn, and SnO are analyzed by found by the XPS and DLTS. The device fabrication using Zn-Si alloy and supercritical carbon dioxide fluid technology has the potential to reduce the process temperature and to improve the memory property of nonvolatile memory device.

This study is focuses on the resistance switching physical mechanism in hafnium oxide (HfO2) of resistive random access memory (RRAM). HfO2 was taken as the resistance switching layer because HfO2 is extremely compatible with the prevalent complementary metal oxide semiconductor (CMOS) process. The detail physical mechanism is studied by the stable RRAM device (Ti/HfO2/TiN), which is offered from Industrial Technology Research Institute (ITRI). In this study, the resistance switching property of two different forming conductions are compared, including DC sweeping forming and AC pulse forming. In general, forming is a pivotal process in resistance random access memory (RRAM) to activate the resistance switching behavior. However, over forming would lead to device damage. The overshoot current has been considered as a degradation reason during the forming process. The circuit design is used to obtain the overshoot effect of DC sweeping forming by oscilloscope and semiconductor parameter analyzer system. The quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultra-fast pulse forming can form a discontinuous conduction path to reduce the operation power.

This diploma thesis presents experimental evidence of a theoretical concept which predicts the self-organization of delta-layers of silicon nanoclusters in the buried oxide of a MOS-like structure. This approach of "bottom-up" structuring might be of eminent importance in view of future semiconductor memory devices. Unconventionally, a 15nm thin SiO2 layer, which is enclosed by a 50nm poly-Si capping layer and the Si substrate, is irradiated with Si+ ions. Ion impact drives the system to a state far from thermodynamic equilibrium, i.e. the local composition of the target is modified to a degree unattainable in common processes. A region of SiOx (x<2) - where x is a function of depth - is formed which is not stable. During annealing, the system relaxes towards equilibrium, i.e. phase separation (via spinodal decomposition and nucleation) sets in. Within a certain time window of annealing, the structure of the system matches with a structure similar to the multidot non-volatile memory device, the principal character of which is a 2D layer of Si nanoclusters of ~3nm in diameter which is embedded in a 3D SiO2 matrix at a distance of ~3nm from the Si substrate. The physical mechanisms of ion mixing of the two Si-SiOx interfaces and subsequent phase separation, which result in the desired sample structure, are elucidated from the viewpoint of computer simulation. In addition, experimental evidence is presented based on various methods, including TEM, RBS, and SIMS. Of particular importance is a novel method of Si nanocluster decoration which applies Ge as contrast enhancing element in TEM studies of tiny Si nanoclusters.

Behovet av att analysera volatilt minne från Macintosh-datorer med OS X har blivit allt mer betydelsefull på grund av att deras datorer blivit allt populärare och att volatil minnesanalysering blivit en allt viktigare del i en IT-forensikers arbete. Anledningen till att volatil minnesanalysering blivit allt viktigare är för att det går att finna viktig information som inte finns lagrad permanent på datorns interna hårddisk. Problemet som låg till grunden för det här examensarbetet var att det uppenbart fanns brist på undersökningsmetoder av det volatila minnet för Mac-datorer med OS X.Syftet med detta arbete var därför att undersöka möjligheten att utvinna information från ett volatilt minne från en Mac-dator med OS X genom att kartlägga och bedöma olika undersökningsmetoder. För att göra denna undersökning har litteraturstudier, informella intervjuer, egna kunskaper och praktiska försök genomförts.Slutsatsen blev att möjligheten att utvinna information från det volatila minnet från en Mac-dator med OS X är relativt begränsad. Det största problemet är själva dumpningen av minnet. Många av dumpningsmetoderna som finns att tillgå kräver administrativa rättigheter. Vid analysering av en minnesdump bör man aldrig förlita sig på en analysmetod då olika analysmetoder ger olika resultat som kan vara till nytta för en vidare undersökning av en Mac-dator. / The need to analyze volatile memory on Macintosh computers with OS X has become increasingly important due to the fact that their computers have become more popular and volatile memory analysis has become a more important part of an IT-forensics work. The reason volatile memory analysis has become more important is that it's possible to find information that’s not stored permanently on the computer’s hard drive. The problem that formed the basis for this thesis was that it was obvious there was a lack of methods of investigation of the volatile memory for Macs running OS X.The aim of this work was therefore to investigate the possibility of extracting information from a volatile memory from a Mac computer with OS X by identifying and assessing different methods of investigation. To do this investigation, literature studies, informal interviews, own knowledge and practical attempts have been conducted.It was concluded that the ability to extract information from the volatile memory from a Mac-computer with OS X is relatively limited. The biggest problem is the dumping of the memory. Many of the available dumping methods require administrative rights. When analyzing a memory dump you should never rely on one analyze method since different analyze methods give different results that can be useful for further investigation of a Mac-computer.

abstract: Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of these cations. This dissertation presents electrical characterization results on Cu-SiO2 based PMC devices, which due to the na- ture of materials can be easily integrated into the current Complimentary metal oxide semiconductor (CMOS) process line. Device structures representing individual mem- ory cells based on W bottom electrode and n-type Si bottom electrode were fabricated for characterization. For the W bottom electrode based devices, switching was ob- served for voltages in the range of 500mV and current value as low as 100 nA showing the electrochemical nature and low power potential. The ON state showed a direct de- pendence on the programming current, showing the possibility of multi-bit storage in a single cell. Room temperature retention was demonstrated in excess of 105 seconds and endurance to approximately 107 cycles. Switching was observed for microsecond duration 3 V amplitude pulses. Material characterization results from Raman, X-ray diffraction, Rutherford backscattering and Secondary-ion mass spectroscopy analysis shows the influence of processing conditions on the Cu concentration within the film and also the presence of Cu as free atoms. The results seemed to indicate stress-induced void formation in the SiO2 matrix as the driving mechanism for Cu diffusion into the SiO2 film. Cu/SiO2/nSi based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

abstract: Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices. This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario. The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

abstract: This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015