Multi-core processors have emerged as an effective solution for handling complex tasks that cannot be efficiently processed by unicore processors. Their usage is driven by the potential to achieve high processing power while minimizing power consumption. However, the conventional multi-core hardware design poses a major challenge in the real-time community due to its inability to provide strict timing guarantees. Customized hardware platforms can be utilized to achieve timing predictability, but they are expensive and difficult to obtain. A cost-effective alternative to customized platforms is commercial-off-the-shelf (COTS) products, which are universal and easily accessible, but they still suffer from timing unpredictability. To address this, memory-centric scheduling can be employed by partitioning the total task execution into distinct memory and computation phases and restricting shared memory access to be exclusive. This study presents a 3-phase task execution framework on the RP2040 multi-core platform to eliminate memory contention and ensure predictable application development. The framework uses custom memory management for each core, specified by the linker script, and a template is provided to create tasks compliant with the phased execution. Four kernel benchmarks, created from the TACLeBench benchmark suite, are used to evaluate the framework. The tasks are statically scheduled and run for ten hyperperiods. The results indicate that the custom memory configuration achieves a setup where no contested accesses occur, resulting in no unexpected variations in total task execution timing, thereby achieving timing predictability on an RP2040. / Flerkärniga processorer har visat sig vara en effektiv lösning för att hantera komplexa uppgifter som inte kan behandlas effektivt av enkärniga processorer. Användningen av dem drivs av möjligheten att uppnå hög bearbetningskapacitet samtidigt som strömförbrukningen minimeras. Den konventionella hårdvarudesignen för flerkärniga processorer utgör dock en stor utmaning för realtidssamhället på grund av dess oförmåga att ge strikta tidsgarantier. Anpassade hårdvaruplattformar kan användas för att uppnå förutsägbarhet i fråga om tidtabell, men de är dyra och svåra att få tag på. Ett kostnadseffektivt alternativ till skräddarsydda plattformar är COTSprodukter (Commercial-off-the-shelf), som är universella och lättillgängliga, men som fortfarande lider av oförutsägbarhet i fråga om timing. För att lösa detta kan man använda minnescentrerad schemaläggning genom att dela upp den totala utförandet av uppgiften i olika minnes- och beräkningsfaser och begränsa åtkomsten till delat minne till att vara exklusiv. I den här avhandlingen presenteras ett ramverk för trefasigt uppgiftsutförande på RP2040-plattformen med flera kärnor för att eliminera minneskonflikter och säkerställa förutsägbar programutveckling. Ramverket använder anpassad minneshantering för varje kärna, som specificeras av länkningsskriptet, och en mall tillhandahålls för att skapa uppgifter som är förenliga med den fasvisa utförandet. Fyra kärnreferensmärken (benchmarks), som skapats från TACLeBench benchmark suite, används för att utvärdera ramverket. Uppgifterna är statiskt schemalagda och körs under tio hyperperioder. Resultaten visar att den anpassade minneskonfigurationen ger en inställning där inga ifrågasatta åtkomster förekommer, vilket resulterar i inga oväntade variationer i den totala tidsåtgången för utförandet av uppgifterna, vilket gör att tidsåtgången är förutsägbar på en RP2040.

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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Current changes in the way that large flight test systems are utilized have affected the industry’s methodology in both the early design phases and in the implementation of nextgeneration hardware and software. The reduction of available RF spectrum, the implementation of packet telemetry methods and systems, and a desire to implement commercial-off-the-shelf (COTS) hardware are only some of the considerations that telemetry systems integrators and product houses have to face. This paper describes how test methodology changes affect current large systems design at both government test ranges and at airframe/missile manufacturer test facilities. In addition, consideration is given to the area of increased processing power as it affects hardware and software design, the leveraging of such current and future telecommunications technology as network switch technology and compression, cross utilization, standardized technology, and the movement toward platform-independent software.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Today’s telemetry systems can reduce spectrum demand and maintain secure voice by encoding analog voice into digital data using; Continuously Variable Slope Delta Modulation ( CVSD ) format and imbedding it into a telemetry stream. The model CSC-0390 DvD system is an excellent choice in decoding digital voice, designed with flexibility, efficiency, and simplicity in mind. Flexibility in design brings forth a capability of operating on a wide variety of telemetry systems and data formats without any specialized interfaces. The utilization of 74HC series circuit technology makes this DvD system efficient in design, low cost, and lower power consumption. In addition the front panel display and control function is also is an example of Simplicity in design and operation.

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The US Government originally funded the development of the Common Airborne Instrumentation System (CAIS) to address industry-wide compatibility, maintenance, and commonality issues. Although initially targeted for US Department of Defense (DoD) programs, CAIS is also being used throughout the world in many commercial applications. This paper provides a fresh look at the evolution of the CAIS concept starting with some historical background of the CAIS Program, an overview of the CAIS System Architecture and recent trends in the use of “Commercial Off The Shelf (COTS)” products and technology.

Approved for public release, distribution is unlimited / This study identifies factors affecting the performance of commercial-off-the-shelf speech recognition software (SRS) when used for ship control purposes. After a review of research in the feasibility and acceptability of SRS-based ship control, the paper examines the effects of: "A restricted vocabulary versus a large vocabulary," Low experience level conning officers versus high experience level conning officers, "Male versus female voices," Pre-test training on specific words versus no pre-test training. Controlled experimentation finds that: "The experience level of a conning officer has no significant impact on SRS performance." Female participants experienced more SRS errors than did their male counterparts. However, in this experiment, only a limited number of trials were available to assess a difference. "SRS with restricted vocabulary performs no better than SRS with large vocabularies." Using the software "correct as you go" feature may impact software performance. Following the user profile establishment, individual user training on two specific words reduces error rates significantly. This study concludes that SRS is a viable technology for ship control and merits further testing and evaluation. / Lieutenant, United States Navy

Background: With increasing clinical use of NK-92 cells and their CAR-modified derivatives in cancer immunotherapy, there is a growing demand for efficient production processes of these “off-the-shelf” therapeutics. In order to ensure safety and prevent the occurrence of secondary tumors, (CAR-)NK-92 cell proliferation has to be inactivated before transfusion. This is commonly achieved by gamma irradiation. Recently, we showed proof of concept that low energy electron irradiation (LEEI) is a new method for NK-92 inactivation. LEEI has several advantages over gamma irradiation, including a faster reaction time, a more reproducible dose rate and much less requirements on radiation shielding. Here, LEEI was further evaluated as a promising alternative to gamma irradiation yielding cells with highly maintained cytotoxic effector function. Methods: Effectiveness and efficiency of LEEI and gamma irradiation were analyzed using NK-92 and CD123-directed CAR-NK-92 cells. LEE-irradiated cells were extensively characterized and compared to gamma-irradiated cells via flow cytometry, cytotoxicity assays, and comet assays, amongst others. Results: Our results show that both irradiation methods caused a progressive decrease in cell viability and are, therefore, suitable for inhibition of cell proliferation. Notably, the NKmediated specific lysis of tumor cells was maintained at stable levels for three days postirradiation, with a trend towards higher activities after LEEI treatment as compared to gamma irradiation. Both gamma irradiation as well as LEEI led to substantial DNA damage and an accumulation of irradiated cells in the G2/M cell cycle phases. In addition, transcriptomic analysis of irradiated cells revealed approximately 12-fold more differentially expressed genes two hours after gamma irradiation, compared to LEEI. Analysis of surface molecules revealed an irradiation-induced decrease in surface expression of CD56, but no changes in the levels of the activating receptors NKp46, NKG2D, or NKp30. Conclusions: The presented data show that LEEI inactivates (CAR-)NK-92 cells as efficiently as gamma irradiation, but with less impact on the overall gene expression. Due to logistic advantages, LEEI might provide a superior alternative for the manufacture of (CAR-)NK-92 cells for clinical application.

Approved for public release; distribution in unlimited. / This thesis represents a cross Systems Command (NAVSEA/NAVAIR) developed product. The product - the Sunset Supply Base (SSB) system - provides a complete system for addressing the risks and supportability issues involved with Commercial Off the Shelf (COTS) products in Navy combat and support systems. The SSB system was implemented on three Navy combat weapon systems at various phases of the product development life cycle. The main body provides to the Program Management Offices (PMO) and other decision makers, a high level summary of performance expectations. Appendix A - The Sunset Supply Base Architecture - identifies at a high level of abstraction a collaborative architecture providing a roadmap for design and development of the SSB system. Appendix B - The Systems Engineering Development and Implementation (SEDI) plan - is a prescriptive or "How to" manual describing activities that have been used to successfully implement the SSB system. Appendix C - Business Case Analysis (BCA) - presents the data collected as a result of SEDI plan implementation then addresses the business/programmatic attributes showing the viability and value proposition possible through the SSB system. Appendix D - The Marketing Plan for the SSB system - defines methods and practices necessary to establish the SSB system as the alternative of choice. / Chemical Engineer, United States Navy / Systems Engineer, United States Navy

Thesis (Master of Business Administration) -- Naval Postgraduate School, 2005. / Title from title screen (viewed Aug. 26, 2008). "December 2005." The original document contains color images. "ADA443358"--URL. Includes bibliographical references (p. 85-91). Also issued in paper format.

CubeSat missions needs components that are tolerant against the radiation in space. The hardware components must be reliable, and it must not compromise the functionality on-board during the mission. At the same time, the cost of hardware and its development should not be high. Hence, this thesis discusses the design and development of a CubeSat architecture using a Commercial Off-The- Shelf (COTS) Multi-Processor System on Chip (MPSoC). The architecture employs an affordable Rad-Hard Micro-Controller Unit as a Supervisor for the MPSoC. Also, it uses several radiation mitigation techniques such as the Latch-up protection circuit to protect it against Single-Event Latch-ups (SELs), Readback scrubbing for Non- Volatile Memories (NVMs) such as NOR Flash and Configuration scrubbing for the FPGA present in the MPSoC to protect it against Single-Event Upset (SEU)s, reliable communication using Cyclic Redundancy Check (CRC) and Space packet protocol. Apart from such functionalities, the Supervisor executes tasks such as Watchdog that monitors the liveliness of the applications running in the MPSoC, data logging, performing Over-The-Air Software/Firmware update. The thesis work implements functionalities such as Communication, Readback memory scrubbing, Configuration scrubbing using SEM-IP, Watchdog, and Software/Firmware update. The execution times of the functionalities are presented for the application done in the Supervisor. As for the Configuration scrubbing that was implemented in Programmable Logic (PL)/FPGA, results of area and latency are reported. / CubeSat-uppdrag behöver komponenter som är toleranta mot strålningen i rymden. Maskinvarukomponenterna måste vara pålitliga och funktionaliteten ombord får inte äventyras under uppdraget. Samtidigt bör kostnaden för hårdvara och dess utveckling inte vara hög. Därför diskuterar denna avhandling design och utveckling av en CubeSatarkitektur med hjälp av COTS (eng. Custom-off-The-Shelf) MPSoC (eng. Multi Processor System-on-Chip). Arkitekturen använder en prisvärd strålningshärdad (eng. Rad-Hard) Micro-Controller Unit(MCU) som Övervakare för MPSoC:en och använder också flera tekniker för att begränsa strålningens effekter såsom kretser för att skydda kretsen från s.k. Single Event Latch-Ups (SELs), återläsningsskrubbning för icke-volatila minnen (eng. Non-Volatile Memories) NVMs som NOR Flash och skrubbning av konfigurationsminnet skrubbning för FPGA:er i MPSoC:en för att skydda dem mot Single-Event Upsets (SEUs), och tillhandahålla pålitlig kommunikation mha CRC och Space Packet Protocol. Bortsett från sådana funktioner utför Övervakaren uppgifter som Watchdog för att övervaka att applikationerna som körs i MPSoC:en fortfarande är vid liv, dataloggning, och Over- the-Air-uppdateringar av programvaran/Firmware. Examensarbetet implementerar funktioner såsom kommunikation, återläsningsskrubbning av minnet, konfigurationsminnesskrubbning mha SEM- IP, Watchdog och uppdatering av programvara/firmware. Exekveringstiderna för utförandet av funktionerna presenteras för den applikationen som körs i Övervakaren. När det gäller konfigurationsminnesskrubbningen som implementerats i den programmerbara logiken i FPGA:n, rapporteras area och latens.