Abstract The thesis is aimed to analyze the flip chip in chip scale package (CSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The coefficient of thermal expansion (CTE) of underfill and different mechanical properties of four kinds underfill-A, B, C, D and with/without metal cap are considered as parameters. The effects of above-mentioned parameters on package¡¦s displacement, strain and stress fields are studied. The results show that the maximum equivalent strain and stress take place at the interface between chip and underfill far away from the center of the whole package and on the top of the most outside solder bump in the solder joint. The larger the CTE of underfill is, the larger the maximum equivalent strain and stress are. Package with metal cap can reduce the displacement to almost half or more of that without cap, but increase the values of maximum equivalent strain and stress. No matter with metal cap or not, the underfill D is the best choice. Hence, the underfill material properties possess lower CTE and larger Young¡¦s modulus than those of solder bump.

Recently, there is a growing interest in applying electronic circuit design for biomedical applications, especially in the area of nuclear magnetic resonance (NMR). NMR has been used for many years as a spectroscopy technique for analytical chem- istry. Previous studies have demonstrated the design and fabrication of planar spiral inductors (microcoils) that serve as detectors for nuclear magnetic resonance mi- crospectroscopy. The goal of this research was to analyze, design, and test a prototype integrated sensor, which consisted of a similar microcoil detector with analog components to form a multiple-channel front-end for a magnetic resonance imaging (MRI) system to perform microspectroscopy. The research has succeeded in producing good function- ality for a multiple-channel sensor. The sensor met expectations compared to similar one-channel systems through experiments in channel separation and good signal-to- noise ratios.

The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management aspects of communication synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core interface redesign, requires the development of a Core-Network Interface (CNI) which allows them to communicate over the on-chip network. The absence of intelligence amongst the NoC components, entails the introduction of a CNI capable of not only providing basic packetization and depacketization, but also other essential services such as reliability, power management, reconguration and test support. A generic CNI architecture providing these services for NoCs is proposed and evaluated in this dissertation. Rising on-chip communication power costs and reliability concerns due to these, motivate the development of a peak power management technique that is both scalable to dierent NoCs and adaptable to varying trac congurations. A scalable and adaptable peak power management technique - SAPP - is proposed and demonstrated. Latency and throughput improvements observed with SAPP demonstrate its superiority over existing techniques. Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con- dence in the correct operation of on-chip cores. The rising design complexity and IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line scheme capable of managing IP core test in the presence of executing applications is essential. Such a scheme ensures application performance and system power budgets are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT) for NoC-based systems and demonstrates how a robust implementation of COLT using a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct operation of the SoC.

With the progress in VLSI technology, the external environment makes it easier for the interference affected the operation of microcontroller. The design of the recently microcontroller, not only the pursuit of speed and performance, also began the study of the various fault-tolerant technology to enhance the reliability and safety. This thesis, being designed for the Fault-tolerant microcontroller according market, presents a Robust Micro-Control Unit : RMCU for dual core architecture of ARM9 ISA. The RMCU provides two operation modes: synchronize mode and Processor test mode for fault-tolerant mechanism. In synchronize mode, both processors are executing the same program concurrently. The results generated by processors are compared, and every mismatch indicates a transient fault in one of the two processors. When the transient fault occurred, the two processors will use Instruction retry mechanism, recover system operation. If the same address's errors larger than the number of settings are considered permanent fault, processors will be held, and entered the processor test mode for processor functional test. In accordance with the test results to close the wrong processor and operating system back to normal. This approach to solve the traditional dual-core processor fault-tolerant architecture that can not be fixed to permanent-fault restrictions. In addition to the design of fault-tolerance mechanism, for the upgrading of software and hardware development and validation of this paper design of the RMCU debug platform. RMCU debug platform including JTAG-based OCD (On-Chip Debugging) unit, and debug interface program. In addition to providing read and write registers and memory, set Breakpoint, Watchpoint and single-step but also take the initiative to increase the external interrupt inserted to provide a more effective ISR (Interrupt Service Routine) debug. In the last of the thesis, we use the FPGA Implementation of the RMCU fault-tolerant mechanisms and debug platform. After simulation and testing, the results prove the feasibility of RMCU.

Due to advancement of semiconductor technology, a system can be designed in a single chip, we call it a system on chip (SOC). An SOC usually reuses silicon intellectual properties (SIP). This speeds up design time and increase correctness of the chip. Memory modules play an important role in an SOC. Under various system requirements, different memory modules should be used. In this research, in order to satisfy various design requirements of memory modules, we designed various advanced and application-specific functional features to be added into memory modules. We planed a configuration method and implemented needed component designs, including fault tolerance, encryption, and allocation. Hence, we can speed up design time and increase design correctness of such memory module designs.

Gegenstand dieser Arbeit sind systematische Untersuchungen zu den Anwendungsmöglichkeiten der am Institut für Physikalische Chemie entwickelten IC-Kalorimeter im Bereich flüssiger Reaktionssysteme, mit Schwerpunkt auf enzymkatalysierten Reaktionen. Dazu kamen IC-Durchfluss- und IC-Batch-Kalorimeter zum Einsatz, mit denen durch Zusammenführung zweier Lösungen initiierte Mischungs- und Reaktionsprozesse untersucht werden können. Anhand einer Vielzahl untersuchter Reaktionssysteme wird unter stofflichen und methodischen Gesichtspunkten aufgezeigt, unter welchen Bedingungen ein Einsatz der IC-Kalorimeter sinnvoll erscheint. Außerdem werden für die miniaturisierten kalorimetrischen Anordnungen spezifische Aspekte diskutiert; u. a. Probleme bei der elektrischen Kalibrierung und die Nachweisgrenzen bzgl. der bei einem zu detektierenden Prozess mindestens zu generierenden Wärme bzw. Wärmeleistung. Beide IC-Kalorimeter konnten durch konstruktive Veränderungen gegenüber vorhandenen Anordnungen in ihrer Leistungsfähigkeit verbessert werden.

Thesis (Ph. D.)--University of California, Riverside, 2009. / Includes abstract. Title from first page of PDF file (viewed March 8, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 123-137). Also issued in print.

The unprecedented demand for performance in the latest technologies will ultimately require changes in the way we design cache. Emerging high density embedded memories such as Spin-Transfer Torque Random Access Memory (STTRAM) have emerged as a possible candidate for universal memory due to its high speed, low power, non-volatility, and low cost. Although attractive, STTRAM is susceptible to contactless tampering through malicious exposure to magnetic field with the intention to steal or modify the bitcell content. In this thesis, we explore various attack techniques on STTRAM and then propose a novel array-based sensor to detect the polarity and magnitude of such attacks and then propose two design techniques to mitigate the attack. With our research, we have been able to successfully implement and accurately detect an attack while providing sufficient compensation window (few ns to ~100 us) to enable proactive protection measures. Finally, we show that variable-strength ECC can adapt correction capability to tolerate failures with various strength of an attack.

Chip multiprocessors (CMPs) commonly share a large portion of memory system resources among different cores. Since memory requests from different threads executing on different cores significantly interfere with one another in these shared resources, the design of the shared memory subsystem is crucial for achieving high performance and fairness. Inter-thread memory system interference has different implications based on the type of workload running on a CMP. In multi-programmed workloads, different applications can experience significantly different slowdowns. If left uncontrolled, large disparities in slowdowns result in low system performance and make system software's priority-based thread scheduling policies ineffective. In a single multi-threaded application, memory system interference between threads of the same application can slow each thread down significantly. Most importantly, the critical path of execution can also be significantly slowed down, resulting in increased application execution time. This dissertation proposes three mechanisms that address different shortcomings of current shared resource management techniques targeted at multi-programmed workloads, and one mechanism which speeds up a single multi-threaded application by managing main-memory related interference between its different threads. With multi-programmed workloads, the key idea is that both demand- and prefetch-caused inter-application interference should be taken into account in shared resource management techniques across the entire shared memory system. Our evaluations demonstrate that doing so significantly improves both system performance and fairness compared to the state-of-the-art. When executing a single multi-threaded application on a CMP, the key idea is to take into account the inter-dependence of threads in memory scheduling decisions. Our evaluation shows that doing so significantly reduces the execution time of the multi-threaded application compared to using state-of-the-art memory schedulers designed for multi-programmed workloads. This dissertation concludes that the performance and fairness of CMPs can be significantly improved by better management of inter-thread interference in the shared memory resources, both for multi-programmed workloads and multi-threaded applications. / text

Off-chip interconnection networks provide for communication between processors and components within computer systems. Semiconductor process technology trends have led to the inclusion of multiple processors and components onto a single chip and recently research has focused on interconnection networks, on-chip, to connect them together. On-chip networks provide a scalable, high-bandwidth interconnect, integrated tightly with the microarchitecture to achieve high performance. On-chip networks present several new challenges, different from off-chip networks, including tighter constraints in power, area and end-to-end latency. In this dissertation, I propose interconnection network architectures that address the unique design challenges of power and end-to-end latency on chip. My work in the design, implementation and evaluation of the on-chip networks of the TRIPS project’s prototype processor, a real hardware implementation, is the foundation for my work in on-chip networking. Based on my analysis of the TRIPS on-chip networks and their workloads, I propose, design, and evaluate novel network architectures for congestion monitoring and adaptive routing that are matched to the design constraints of on-chip networks. In the TRIPS system we designed, and implemented in silicon, a distributed processor microarchitecture where traditional processor components are divided into a collection of self-contained tiles. One novel aspect of the TRIPS system is the control and data networks that the tiles use to communicate with one another. I worked on the design and implementation of one of these networks, the On-Chip Network (OCN). The OCN, a 4x10 mesh network, interconnects the tiles of the L2 cache, the two processor cores and various I/O units. Another on-chip network, the Operand Network (OPN), interconnects the execution units and serves as a bypass network, integrated tightly with the processor core. In this document I evaluate these two on-chip networks and their workloads, these evaluations serve as case studies in how on-chip design constraints affect the design of on-chip networks. In the examination of the TRIPS OCN and OPN networks, one insight we gained was that network resource imbalances can lead to congestion and poor performance. We found these imbalances are transient with time and task. Timely information about the status of the network can be used to balance the resource utilization, or reduce power. A challenge lies in providing the right information, conveyed in a timely fashion, as the metrics and methods used in off-chip networks do not map well to on-chip networks. In this document, I propose and evaluate several metrics of network congestion for their utility and feasibility in an on-chip environment. In our examination of the TRIPS on-chip networks we also found that minimizing end-to-end packet latency was critical to maintaining good system performance. Effective use of the congestion information without impact to end-to-end latency is another challenge in on-chip networking. I explore novel adaptive routing techniques that address the challenge of managing the end-to-end latency. A method that produces good results is aggregation of network status information, reducing both the bandwidth and latency required for status information transmission. In this dissertation I examine how well this technique and others compare with conventional oblivious and adaptive routing. / text