This paper states the stability requirements of the amplifier system, and then presents, and summarizes, the classic two stage CMOS Op-Amp design by employing several popular frequency compensation techniques including traditional Miller compensation, nulling resistor, voltage buffer, and current buffer. The advantages and disadvantages of all these compensation strategies are evaluated based on a standard performance which has a 70dB DC gain, a 60◦ phase margin, a 25MHz gain bandwidth, and a slew rate of 20 V/us requirements. All the designs and simulation results are based on a 180mm 1.8 V standard TSMC CMOS technology. Ultimately, the traditional Miller compensated Op-Amp (a single compensation capacitor amplifier) cannot meet all the requirements but all other techniques could with also a boost of performance in various aspects. / Master of Science / Two-stage CMOS operational amplifier has two input pins and one output pin. it is used to amplify the differential inputs signal and transfer it to the output side. Usually the input signals are too weak to be processed by the rest of the system units. So the Op-Amp can amplify the weak input signals which then can either be further modified for some specific applications by the rest units of the system or be the final output of this entire system. The role of the Op-Amp in analog and digital systems is as the role of transformers in the power system. So the output signal is required to have fast and stable responses to the inputs. This paper states some standard requirements of the Op-Amp in aspects of gain, stability, and operating frequency. Due to the classic design of two-stage Op-Amp has poor performance of stability and operating frequency, some compensation techniques are applied as the feedback networks to improve its performance. These techniques include traditional Miller compensation, nulling resistor, voltage buffer, and current buffer. The advantages and disadvantages of all these compensation strategies are evaluated based on a 180mm 1.8 V standard TSMC CMOS technology.

One of the most critical blocks in a wide-band continuous time sigma delta (CTSD) analog-to-digital converter (ADC) is the loop filter. For most loop filter topologies, the performance of the filter depends largely on the performance of the operational amplifiers (op-amps) used in the filter. The op-amps need to have high linearity, low noise and large gain over a wide bandwidth. In this work, the impact of op-amp parameters like noise and linearity on system level performance of the CTSD ADC is studied, and the design specifications are derived for the op-amps. A new class-AB bias scheme, which is more robust to process variations and has an improved high frequency response over the conventional Monticelli bias scheme, is proposed. A biquadratic filter which forms the input stage of a 5th order low pass CTSD ADC is used as a test bench to characterize the op-amp performance. The proposed class-AB output stage is compared with the class-AB output stage with Monticelli bias scheme and a class-A output stage with bias current reuse. The filter using the new op-amp architecture has lower power consumption than the other two architectures. The proposed class AB bias scheme has better process variation and mismatch tolerance compared to the op-amp that uses conventional bias scheme.

This work describes the implementation of DC to DC converter for Smart Dust in 65 nm CMOS technology. The purpose of a DC to DC converter is to convert a battery voltage of 1 Vto a lower voltage of 0.5 V used by the processor. The topology used in this DC to DC converteris of Buck type which converts a higher voltage to lower voltage with the advantage of givinghigh efficiency about 75%. The system uses PWM (Pulse width modulation) technique. It usesnon-overlapping clock generation technique for reducing the power consumption. The systemprovides up to 5 mA load current and has power consumption of 2.5 mW.

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator.

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator.

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level.

Industrial systems often require the acquisition of real-world analog signals for several applications. Various physical phenomena such as displacement, pressure, temperature, light intensity, etc. are measured by sensors, which is a type of transducer, and then converted into a corresponding electrical signal. The electrical signal obtained from the sensor, usually a few tens mV in magnitude, is subsequently conditioned by means of amplification, filtering, range matching, isolation etc., so that the signal can be rendered for further processing and data extraction. This thesis presents the design and implementation of a general purpose op amp used to condition a reflective object sensor’s output. The op amp is used in a non-inverting configuration, as a current-to-voltage converter to transform a phototransistor current into a usable voltage. The op amp has been implemented using CMOS architecture and fabricated in AMI 0.5-µm CMOS process available through MOSIS. The thesis begins with an overview of the various circuits involving op amps used in signal conditioning circuits. Owing to the vast number of applications for sensor signal conditioning circuits, a brief discussion of an industrial sensor circuit is also illustrated. This is followed by the complete design of the op amp and its implementation in the data acquisition circuit. The op amp is then characterized using simulation results. Finally, the test setup and the measurement results are presented. The thesis concludes with an overview of some possible future work on the sensor-op amp data acquisition circuit.

The goal of this thesis is create measuring station of resolver with using Analog Devices AD2S1210. The measuring station is based on the Atmel ATmega16 microprocesor and programmed in the C language. The measuring plant of resolvers to detection fault per one revolution is developed with industrial cooperation. The measuring station is made for a mobile use with onboard Pb accu. Measuring station will be used as a service device or in the manufacturing for setting the right angle of resolver on the engine. For the faults debugging of resolvers cables and other faults with the signal chain between the resolver and AD2S1210 is possible to show the SIN and COS signals on the external scope.

A need for high bandwidth operational amplifiers, or op-amps, exists for certain applications. This need requires research in the area of op-amp bandwidth extension. The proposed method of this thesis uses Negative Capacitance Generation (NCG), which involves using the Miller effect to generate an equivalent negative capacitance at a given node in a circuit, to extend the bandwidth of an op-amp. This is accomplished by first applying NCG to the second stage of an op-amp, in which the op-amp has been compensated using Single Capacitor Miller Compensation (SCMC). Next, the Miller capacitor used to compensate the op-amp can be reduced and thus, the bandwidth of the op-amp is extended. The proposed method employed a 100dB, classic two-stage op-amp with a 7.7MHz gain-bandwidth product (GBW). It was discovered that after applying NCG to several places in the op-amp besides the second stage that the GBW was roughly doubled. The GBW of the second stage was improved by a factor of 9.3. This discrepancy in GBW improvements was researched and certain barriers were discovered. Although the barriers were not eliminated, research in overcoming them and obtaining greater improvements in op-amp bandwidth is encouraging.

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level.