Abstract The tendency to manufacture of semiconductor is to minimize the size of device. With the size was minimized, the number of transistor on the chip was maximized at the same time .However, when the drift region of Power-MOSFET is shorter will result in the Breakdown Voltage is lower, so this do not conform our purpose for application, and therefore we should look for some alternative method to enhance efficiency. One of these method of efficiency promotion is adopting channel strain. We adopt bending silicon substrate to obtain strain. By using this method, we successfully enhance drain current and mobility 12.1% and 4.1% individually. Furthermore, regarding the reliability study, we realize the hot-carrier effect influence under strain silicon. The longer the size(Lg & DL) of Power- MOSFET , the reliability is better. When device were bent under Bending R=40mm and Lg=0.8(m conditions, we can obtain the better reliability of device than flat chip.

With the use of the simplistic equivalent circuits, loss mechanism in conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate drive circuits is analyzed. Resonant gate drive techniques are investigated and a new resonant gate drive circuit is presented. The presented circuit adds minor complexity to conventional gate drivers but reduces the MOSFET gate drive loss very effectively. To further expand its use in driving Half-Bridge MOSFETs, another circuit is proposed in this thesis. The later circuit simplifies the isolation circuitry for the top MOSFET and meanwhile consumes much lower power than conventional gate drivers. / Master of Science

In modern power electronics systems there is a growing trend to replace discrete devices with integrated power electronic modules (IPEMs). In this way, several components can be replaced by a single component. By using prefabricated building blocks, the engineer simplifies the design process, reducing the total design cycle time and cost. By integrating only the necessary components to provide power switching, the end user has a pre-optimized building block with the flexibility to be used in a large variety of applications. Besides simplifying the design process, power modules should be designed in such a way as to improve the performance of the power converter. This begs the question as to how best to judge if one IPEM has better performance than another or better performance than its discrete counterpart. In analyzing a converter's performance, popular criteria include efficiency, power density, device stresses, and EMI. All of these criteria are strongly linked to the switching characteristics of the IPEM's power devices. This thesis is a comprehensive study of the requirements for obtaining and analyzing the switching characteristics of the IPEM's power devices. It outlines the important switching characteristics and the implications of each characteristic on converter performance. It deals with the relevant measurement issues, specifically addressing the minimum requirements, which sensors are most suitable, and problems leading to inaccurate data. A parametric study is conducted to determine the effects of several circuit and operating parameters on the switching characteristics. Using the resulting data and the knowledge from the measurement study, we can decide how to design the testbed layout, what operating conditions should be chosen for testing, and what effects of the tester must be decoupled to truly see the effects of IPEM design. The thesis concludes with the design of standard test equipment and procedures. / Master of Science

<p>Advances in modern technology and recent demand for high power applications have motivated great interest in power electronics. Power semiconductor devices are key components that have enabled significant advances in power electronic systems. Historically, silicon has been the material of choice for power semiconductor devices such as diodes, transistors and thyristors. However, silicon devices are now reaching their fundamental limits, and a transition to wide bandgap semiconductors is critical to make further progress in the field. Among them, SiC (silicon carbide) has attracted increasing attention as a power semiconductor to replace silicon due to its superior properties and technological maturity. In fact, SiC power MOSFETs have been commercially available since 2011, and are actively replacing their silicon counterparts at blocking voltages above 1 kV. At these voltages, the specific on-resistance of SiC MOSFETs is 200-300x lower than that of silicon devices. However, conventional vertical SiC MOSFETs are still far from their theoretical performance at blocking voltages below 2 kV. In this regime, the channel resistance is the dominant limitation due to the relatively low channel mobility at the SiO2/4H-SiC MOS interface.<br></p><p> </p><p>In this thesis, the first successful demonstration of a novel power device in 4H-SiC called the trigate power DMOSFET (double diffused metal oxide semiconductor field effect transistor) is presented. This device reduces the channel resistance by a factor of 3-5× compared with the state-of-art commercial power DMOSFETs, without requiring an increase in the channel mobility. The trigate structure is applied to a power MOSFET for the first time along with a self-aligned short channel process. This new structure utilizes both the conventional horizontal surface as well as the sidewalls of a trench to increase the effective width of the channel without increasing the device area. Conceptual design, optimization, process development and electrical results are presented. The trigate power MOSFET with a trench depth of 1 μm designed for a blocking voltage of 650 V has a specific on-resistance of 1.98 mΩcm²and a channel resistance of 0.67 mΩcm².This corresponds to a ∼2× reduction in the total specific on-resistance, and a 3.3× reduction in the specific channel resistance as compared to a conventional DMOSFET with the same blocking voltage rating. This demonstration is a landmark that could help SiC technology compete successfully in the lower blocking voltage regime below 600 V, and access for the first time a completely new segment in the power electronics application space.</p>

Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.

Switching device power losses place critical limits on the design and performance of high-frequency integrated DC-DC converters. Especially, the layout of metal interconnects in lateral power MOSFETs has a profound effect on their on-resistances and conduction power losses. This thesis presents an analytical interconnect modeling and layout optimization technique for large-area power MOSFETs. The layout optimization of 24V LDMOS transistors in the area of 1 mm2 has achieved an improvement of 55 % in its on-resistance. The simulation result has been verified by experimental measurements on a test chip fabricated in TSMC 0.25 µm HV CMOS technology. In addition, this thesis presents an optimized output stage design methodology for the implementation of a 4 MHz, 12V to 1V integrated DC-DC converter. A segmented output stage scheme is employed to increase the converter efficiency at light load conditions. The peak efficiency of 84% was achieved at load current of 2 A.

<p>Increasing demand for higher power density in many applications such as Hybrid Electric Vehicles (HEVs) and renewable power generation has led to great technological advances in power electronics. To meet this increasing demand, a power semiconductor device needs to have low on resistance, increased switching speeds and reduced total system cost. Silicon (Si) power devices have been used for several decades but they are fundamentally limited by material properties. Silicon carbide (SiC) as a power semiconductor material offers superior electrical and thermal properties compared to silicon, which it can replace in a large spectrum of applications. Because of a lower critical electric field, drift regions in Si power transistors need to be much thicker and more lightly doped, which in turn increases the specific onresistance Ron,sp. To combat the drift resistance component for higher blocking voltages, superjunction MOSFETs for medium voltages and Si IGBTs for high voltages are used. Since IGBTs are bipolar transistors, they exhibit much higher switching energy losses than MOSFETs. The SiC MOSFET is an excellent candidate in the medium to high voltage range, which mainly targets the HEV market.</p><p><br></p><p>Due to their low channel mobility, SiC MOSFETs have not reached the theoretical limit below 1200 V where channel resistance is dominant. Planar DMOSFETs dominate the</p><p>commercial SiC market today because of higher yield and relatively simpler fabrication process, but trench MOSFETs can be made with a smaller cell area and thus lower Ron,sp. Due to lower cell-pitch and high integration density of trench-gate devices, they offer an opportunity to reduce the size and weight of HEV power control units by replacing IGBTs with MOSFETs. The single-trench UMOSFET was first reported in 1994 by CREE and the first oxide protected trench MOSFET in 1998 by Purdue. This structure inserts a grounded p-type region below the gate trench to protect the oxide in the blocking state. In 2012, Rohm Semiconductor reported a novel double-trench UMOSFET with separate gate and</p><p>field-protection trenches. In 2017, Infineon published their new trench UMOSFET, known as Cool-SiC, with high gate oxide reliability. In this work a deeply-scaled, fully-self-aligned trench MOSFET is fabricated and characterized. The innovative process described enables a record cell-pitch of 0.5 μm per channel, equivalent to a channel density 6Å~ higher than currently available commercial UMOSFETs.</p>

There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0–40V) and high voltage (40–5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed. / Master of Science

Der Graben-Gate-MOSFET ist eine herausragende Bauelementarchitektur unter den vertikalen Bauelementen auf GaN-Basis, die derzeit für die nächste Generation der Leistungselektronik untersucht werden. Ein niedriges Reststromniveau im Aus-Zustand bei hoher Drain-Spannung ist für vertikale Transistoren von großer Bedeutung, da es ein entscheidendes Merkmal für eine hohe Durchbruchspannung und Zuverlässigkeit der Bauelemente ist. Die Drain-Restströme im Aus-Zustand haben ihren Ursprung in verschiedenen Quellen im vertikalen Trench-Gate-MOSFET. Neben dem Trench-Gate-Modul können auch die Reststrompfade an der trockengeätzten Seitenwand des lateralen Kantenabschlusses erheblich zum Drain-Reststrom im Aus-Zustand beitragen. In diesem Bericht wird der Einfluss jedes relevanten Prozessschritts auf den Drain-Reststrom im Aus-Zustand anhand spezifischer Teststrukturen auf hochwertigem epitaktischem GaN-Material, welche den lateralen Kantenabschluss des MOSFETs nachbilden, untersucht. Die elektrische Charakterisierung zeigt die Empfindlichkeit des Reststroms gegenüber plasmabezogenen Prozessen. Es wird eine Technologie der Randterminierung vorgestellt, die zu einem niedrigen Reststrom führt und gleichzeitig dicke dielektrische Schichten aus plasma-unterstützter Abscheidung enthält, die für die Herstellung einer Feldplattenstruktur über dem Kantenabschluss vorgesehen sind. / The trench gate MOSFET represents a prominent device architecture among the GaN based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

Η ψηφιακή τεχνολογία έχει διεισδύσει πλήρως στην περιοχή της Ακουστικής και της Τεχνολογίας Ήχου, όπως επίσης και σε όλους σχεδόν τους κλάδους της σύγχρονης επιστήμης και της τεχνολογίας. Στον τομέα των ηλεκτρονικών για ηχητικές εφαρμογές, ιδιαίτερα καθοριστικό ρόλο κατέχουν οι ενι- σχυτές. Σκοπός της εργασίας αυτής, είναι να παρουσιάσει το λειτουργικό μοντέλο ενός ψηφιακού ενι- σχυτή Class-D για ηχητικά σήματα, το οποίο προσομοιώθηκε και λειτούργησε σε περιβάλλον Matlab & Simulink. Στο τέλος παρουσιάζονται τα αποτελέσματα χρήσιμων μετρήσεων για σημαντικούς δεί- κτες της ηλεκτροακουστικής όπως η Απόκριση Συχνότητας, Total Harmonic Distortion(THD), Total Harmonic Distortion plus Noise (THD+N) ως προς τη συχνότητα και ως προς την ισχύ, από όπου βγαίνουν συμπεράσματα σχετικά με την ποιότητα και την απόδοση της συγκεκριμένης τεχνολογίας υλοποίησης. / DigitalTechnology has been fully into Acousctics and Audio Technology,as in virtually all branches of modern science and technology.In audio electronics applications, amplifiers have a significant role. The purpose of this thesis is to present the functional model of a digital Class-D amplifier for audio signals, which has been simulated and run in Matlab & Simulink environment. Finally the results of measurements relating to some important electroacoustics indexes like Frequency Response, Total Harmonic Distortion (THD), Total Harmonic Distortion plus Noise (THD+N), relative to the audio signal’s frequency and power, are presented and lead to some conclusions concerning the quality and efficiency of this implementation technology.