L'oxyde de grille des composants peut subir un claquage suite au passage d'un ion lourd unique au travers d'un événement appelé « Single Event Gate Rupture » (SEGR). Dans certains cas, aucune dégradation apparente n'est observée après irradiation bien qu'une interaction ait eue lieu au sein de la couche d'oxyde. Nous parlons alors de la création de défauts latents au sein de la couche isolante. L'objet de cette thèse consiste à évaluer l'impact de ce type de défaut sur la dé-fiabilisation des systèmes de conversion d'énergie embarqués à bord des satellites. En Europe, les principaux maîtres d'œuvre dans la fabrication des satellites se trouvent aujourd'hui face au problème que pose la prise en compte de ces défauts latents. En effet, pour garantir la fiabilité du système de conversion d'énergie, les transistors MOS de puissance doivent suivre une procédure de qualification radiation basée sur la méthode de test militaire américaine MIL-STD-750E/1080. Cette méthode est identique en tout point au standard européen mais recommande en plus, d'effectuer un stress électrique post radiation (Post Gate Stress Test, PGST) afin de révéler la présence d'éventuels défauts latents créés pendant l'irradiation. L'objet de ce travail est d'amener des résultats scientifiques permettant de statuer sur la pertinence du PGST. / At present, space actors are highly concerned with heavy ion-induced power MOSFETs hard failures and in particular by oxide rupture after heavy ion irradiations. In order to guarantee the reliability of space systems, contractors have to follow qualification procedures. The US military standard for heavy ion testing, MIL-STD-750E method 1080, recommends performing a post irradiation test (Post Gate Stress Test PGST) in order to reveal latent defects sites that might have been created during irradiation. Unfortunately, this type of test can only be considered as a pass or fail test. With a too much restrictive approach, rare are the devices to be qualified. Even if the US test method is accurate on most of the points, the main issue is related to the Post-irradiation Gate Stress. What is lacking is that this part of the US Test Standard has neither been dedicated to real space missions nor adapted to space environment. The PGST has even no physical basis justifying performing it for space applications. Working from fundamental to applicative, we aim at drawing test standards dedicated to the engineer in charge of space applications. The qualification of power MOSFETs for space applications is one of the major challenges for European space actors. The goal of this thesis is first to focus on latent defects formation criteria and then, to show under which conditions the post irradiation gate stress test might be relevant or not.

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.

No description available.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第25291号 / 工博第5250号 / 新制||工||1999(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 木本 恒暢, 教授 引原 隆士, 准教授 三谷 友彦, 教授 川上 養一 / 学位規則第4条第1項該当 / Doctor of Agricultural Science / Kyoto University / DFAM

Silicon Carbide as a wide-bandgap semiconductor has several physical and electrical advantages over Silicon for high voltage and high frequency applications. SiC as a MOSFET device has a lot of great characteristics like lower on-resistance and low input capacitances. However, due to its high switching capabilities, SiC MOSFET-based converter circuits experience higher dv/dt and di/dt transients and are therefore more susceptible to parasitic elements. This thesis investigates the interaction of the parasitic gate inductance and resistance on the switching behaviour of SiC DMOSFET (planar) and UMOSFET (trench). To examine this, a double pulse test (DPT) setup was utilised both in simulation and experimentally. The influence of the gate inductance and resistance on the oscillation behaviour in the VGS during the miller period was found to be dependent on the condition of the upper device. Furthermore, the upper device was discovered to have a high impact on the oscillations in the VGS via its source inductance. The gate inductance showed a mixed impact on IDS and VDS overshoot, with IDS overshoot reducing with increasing gate inductance and the reverse case for VDS. The gate resistance, however, showed a consistent impact on both IDS and VDS overshoot, with both reducing with increasing gate resistance. These results ultimately point to the impact of di/dt and dv/dt transients. An interesting result observed on these root causes showed that in the DPT arrangement used, lower test current levels may have a more significant impact on the oscillations in the VGS than higher test current when varying the test currents, with 20 A having the highest impact on the oscillations in simulations and 15 A having the highest impact in experimental verification. On the switching energy, the gate inductance was not shown to have a significant impact on switching losses while the gate resistance had a much more significant impact on the switching losses. / Kiselkarbid som halvledare med brett bandgap har flera fysiska och elektriska fördelar jämfört med kisel för högspännings- och högfrekvensapplikationer. SiC som en MOSFET-enhet har många fantastiska egenskaper som lägre resistans och låga ingångskapacitanser. Men på grund av dess höga omkopplingsförmåga upplever SiC MOSFET-baserade omvandlarkretsar högre dv/dt och di/dt transienter och är därför mer mottagliga för parasitiska element. Denna avhandling undersöker interaktionen mellan gate-drivkretsens parasitära induktans och resistans på kopplingsbeteendet på SiC DMOSFET (plan) och UMOSFET (trench). För att undersöka detta användes en dubbelpulstest (DPT) mätuppställning både i simulering och experimentellt. Inverkan av grindinduktansen och motståndet på svängningsbeteendet i VGS under Millerperioden visade sig vara beroende av den övre anordningens tillstånd. Vidare upptäcktes att den övre anordningen hade en hög inverkan på svängningarna i VGS via dess parasitiska induktans. Gate-induktansen visade en blandad inverkan på IDS- och VDS-översvängning, med IDS-översvängning som minskade med ökande gateinduktans och det omvända fallet för VDS. Gatemotståndet visade dock en konsekvent inverkan på både IDS- och VDS-överskridningar, med båda minskande med ökande gatemotstånd. Dessa resultat pekar slutligen på inverkan av di/dt- och dv/dt-transienter. Ett intressant resultat som observerats på dessa grundorsaker visade att i det använda DPT-arrangemanget kan lägre testströmnivåer ha mer signifikant inverkan på svängningarna i VGS än högre testström vid variation av testströmmarna, med 20 A som har den högsta inverkan på svängningarna i simuleringar och 15 A som har störst effekt vid experimentell verifiering. På omkopplingsenergin visades inte grindinduktansen ha någon signifikant inverkan på omkopplingsförlusterna medan grindresistansen hade mycket mer betydande inverkan på omkopplingsförlusterna.

abstract: In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics. Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide/nitride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide/nitride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors. Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

This master’s thesis deals with active electronic loads focusing mostly on alternating input signals. The principles and modes of both DC and AC loads are described, as well as the most important parameters of MOSFET transistor which is used as the main power component. It deals with designing a regulation circuit of an AC load in detail. This work also discusses the possibilities of realisation of the remaining parts of the device. At the end of the thesis the function of the designed regulation circuit is verified by simple measurements on a prototype.

Les travaux de recherche présentés dans ce mémoire, portent sur la conception et l’étude de MOSFETs de puissance faible tension pour des applications automobiles micro-hybrides de type alterno-démarreur. Pour certaines de ces applications, en plus des modes de fonctionnement standards passant et bloqué, les composants développés doivent être capables de fonctionner en mode d’avalanche à fort courant et à des températures élevées. Pour reproduire en laboratoire ces conditions de fonctionnement, les MOSFETs sont soumis à un test UIS répétitif spécifique. Afin d’évaluer la température du silicium pendant ce test, plusieurs méthodes de mesure de température ont été développées et comparées. En parallèle, un suivi des paramètres électriques standards (BVDSS, IDSS, RDSon…) tout au long du test est effectué, dans le but de déterminer l’impact de l’avalanche répétitive sur le transistor. Seule la RDSon des MOSFETs semble évoluer avec le nombre d’impulsions d’avalanche. Ce phénomène est expliqué par la méthode de mesure de RDSon et par la variation de la résistance du métal source pendant le cyclage. En effet, différentes observations ont permis de constater un vieillissement de la métallisation de source du composant, accompagné d’une modification de sa résistivité. Divers types de métaux et de techniques d’assemblage ont alors été expérimentés pour tenter de limiter cet effet. Aussi des structures de test ont été conçues pour étudier l’évolution du métal et pour pouvoir comparer rapidement le comportement de différentes métallisations / Research work presented in this thesis concern the conception and the study of low voltage power MOSFETs for micro hybrid vehicles (starter alternator). For some of these applications, developed transistors must be able to operate in classical ON and OFF state mode and in avalanche mode at high current and high temperature. To reproduce this operating mode, MOSFETs are submitted to a specific repetitive UIS test. In order to evaluate silicon’s temperature during this test, several temperature measurement methods have been developed and compared. In parallel, in order to understand the impact of repetitive avalanche on the transistor, standard electrical parameters (BVDSS, IDSS, RDSon…) are monitored during the test. The only parameter that seems to be shifting with the number of cycles is the RDSon. This phenomenon is due to the measurement method and to a variation of source metallization resistance during cycling. Indeed several observations have shown source metallization ageing and a shift in its resistivity. Different metallization and assembly parameters have been tested to limit this phenomenon. Also various test structures have been designed to study metallization evolution and to compare different metallization behaviors

No description available.

Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.