COMPARISONS OF ACUTE NEUROMUSCULAR FATIGUE IN MAXIMAL EFFORT STRENGTH TRAINING USING POWERLIFTS. N. T. Theilen, B. I. Campbell, M. C. Zourdos2, J. M. Oliver3, J. O'Halloran1, N. Asher1, J. M. Wilson4 1University of South Florida, Exercise and Performance Nutrition Laboratory, Tampa, FL 2Florida Atlantic University, Boca Raton, FL 3Texas Christian University, Fort Worth, TX 4University of Tampa, Tampa, FL Neuromuscular fatigue is associated with a decrease in velocity. Following powerlift training, the extent to which fatigue affects the performance velocity of each lift after a specified recovery interval has not yet been investigated. Purpose To assess the level of acute neuromuscular fatigue, as measured by a decrease in peak velocity, as a result of maximal effort strength training sessions with each powerlift. Methods Twelve resistance trained males (22.8 ± 2.6 yrs; 177.1 ± 6.7 cm; 83.0 ± 12.6 kgs) participated in a randomized crossover design with three conditions: Squat (SQ), Bench Press (BP), and Deadlift (DL). Subjects' relative strength included the ability to successfully complete at least 1.5x their bodyweight in the squat exercise. Initially, baseline peak velocity (PV) was measured for each lift at 60% 1RM via a TENDO unit. One training session occurred each Monday for 3 consecutive weeks (1 week for each lift). Each training session consisted of a 1RM of the designated lift followed by 4 sets of 2 repetitions at 92.5% and 4 sets of 3 repetitions at 87.5%. Following training sessions, each lift PV was measured at 24, 48, and 72 hours post-training to compare with baseline measures and determine recovery. Data was analyzed using a repeated measures ANOVA (p<.05). Results SQ: No significant differences in PV of the SQ and DL following SQ training at each time point compared to baseline. Bench press PV significantly declined following squat training (Baseline = 1.069 m/s; 24 hours = 0.974 m/s [p = 0.019]; 48 hours = 1.015 m/s [p = 0.034]; 72 hours = 0.970 m/s [p = 0.004]. BP: No significant differences in PV of the SQ and DL following BP training at each time point compared to baseline. Bench press PV significantly declined only at 24 hours following BP training (Baseline = 1.069 m/s; 24 hours = 0.988 m/s [p = 0.004]). DL: No significant differences in PV of the DL following DL training as compared to baseline. Squat PV significantly declined at 24 hours following the DL training (Baseline = 1.384 m/s; 24 hours = 1.315 m/s [p = 0.032]. Similar to SQ, PV of the BP significantly declined only at 24 hours following DL training (Baseline = 1.069 m/s; 24 hours = 0.979 m/s [p < 0.001]). Conclusions Bench press PV was significantly decreased 24-hours following each of the three powerlifts as compared to baseline values. Interestingly, there were no changes in squat and deadlift PV following training of that specific lift. Practical Applications Regardless of the powerlift trained, bench press PV at 60% was compromised 24-hours later. Therefore, following training of any powerlift, more than 24-hours may be needed to optimize performance in the BP at submaximal intensities.

The widespread use of microprocessor chips in high performance applications like graphics simulators and low power applications like mobile phones, laptops, medical applications etc. has made power estimation an important step in the manufacture of VLSI chips. It has become necessary to estimate the power consumption not only after the circuits have been laid out, but also during the design of the modules of the microprocessor at higher levels of design abstraction. The design of a microprocessor is complex and is performed at multiple layers of abstraction before it finally gets manufactured. The processor is first conceptually designed using blocks at the system level, and then modeled using a high-level language (C, C++, SystemC). This enables the early development of software applications using these high-level models. The C/C++ model is then translated to a hardware description language (HDL), that typically corresponds to the register transfer level (RT-Level). Once the processor is defined at the RT-Level, it is synthesized into gates and state elements based on user-defined constraints. In this thesis, novel techniques to estimate the power consumed by the microprocessor circuits at the gate level and RT-level of abstraction are presented. At the gate level, the average power consumed by microprocessor circuits is straight-forward to estimate, as the implementation is known. However, estimating the maximum or peak instantaneous power consumed by the microprocessor as a whole, when it is executing instructions, is a hard problem due to the high complexity of the state space involved. An hierarchical approach to estimate the peak power using powerful search techniques and formal tools is presented in this thesis. This approach has been extended and applied to solve the problem of estimating the maximum supply drop. Details on this extension and a discussion of promising results are also presented. In addition, this approach has been applied to explore the possibility of minimizing the leakage component of power dissipation, when the processor is idle. At the register transfer level, estimating the average power consumed by the circuits of the microprocessor is by itself a challenging problem. This is due to the fact that their implementation is unknown at this level of abstraction. The average power consumption directly depends on the implementation. The implementation, in turn, depends on the performance constraint imposed on the microprocessor. One of the factors affecting the performance of the microprocessor, is the speed of operation of its circuits. Considering these factors and dependencies (for making early design decisions at the RT-Level), a methodology that estimates the power vs. delay curves of microprocessor circuits has been developed. This will enable designers to make design decisions for even rudimentary designs without going through the time consuming process of synthesis. / text

Introduction: Caffeine has long been used to enhance athletic performance. The research regarding caffeine’s effects on strength and power performance is lacking, especially in female athletes. Purpose: To analyze the acute effects of caffeine on jumping performance and maximal strength in female collegiate athletes. Methods: Eight female collegiate athletes performed two testing sessions separated by one week. Using a double-blind approach, athletes randomly received 6 mg/kg of body mass of caffeine (CAF) or a placebo (PLA). Following 60min of quiet sitting and a standardized warm-up, athletes were tested on measures of squat jump height (SJH) and peak power (SJPP), countermovement jump height (CMJH) and peak power (CMJPP), and isometric mid-thigh pull peak force (IPF) and rate of force development (RFD) on force platforms. Heart rate, systolic blood pressure, diastolic blood pressure, and tympanic temperature were measured at three time points across the testing session. A paired samples t-test with Hedge’s g effect size was used to compare performance results between conditions. A 2 x 3 (condition x time) repeated measures ANOVA was used to analyze changes in physiological measures between and within conditions. Alpha level for all analyses was set at pResults: There were small to moderate differences in SJH (p=0.08, g=0.26), SJPP (p=0.03, g=0.63), CMJH (p=0.004, g=0.27), CMJPP (p=0.18, g=0.20), IPF (p=0.08, g=0.25), and RFD (p=0.22, g=0.40) in favor of caffeine over placebo. Physiological measurements increased similarly across time for both conditions with the exception of SBP, which was greater following caffeine 3 administration compared to placebo (p=0.02). Conclusions: Caffeine ingestion produced small to moderate improvements in jumping performance; however, caffeine failed to significantly affect maximal strength when compared with the placebo. Nonetheless, there was a small increase in IPF and RFD compared to placebo. Therefore, caffeine appears to be an effective ergogenic aid when used to enhance jumping performance and possibly maximal strength in female collegiate athletes.

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This dissertation addresses the issues of high power consumption and verification associated with a novel hardware design methodology based on high-level synthesis using action-oriented specifications. High-level synthesis of hardware designs is the process of automatically converting high-level behavioral specifications of designs into their corresponding RTL (Register Transfer Level) descriptions. From a designer's perspective, writing high-level specifications of a design alleviates the burden of handling various scheduling and concurrency issues, which can be automatically handled by the high-level synthesis tool. In the recent past, EDA (Electronic Design Automation) industry has seen efforts by various vendors to make such synthesis process practical for generating efficient hardware designs. In most of these cases, the inputs to high-level synthesis tools are the control data-flow graphs (CDFGs) or hierarchical variants of those. These models sequentialize parts of the computation in the form of computation threads. In contrast, in the last couple of years, advances have been made in an alternative high-level hardware design methodology where the specifications are action-oriented rather than the composition of sequential threads. In this paradigm, a hardware design is described in terms of atomic actions and then synthesized into the RTL code. Action-oriented synthesis process inherently targets the reduction of area and latency of a hardware design. However, two important issues that have not been addressed adequately are (1) power optimizations during such synthesis and (2) verification of action-oriented specifications and synthesized power-minimized implementations of the designs. With the proliferation of power-hungry portable devices, ever shrinking geometries and increasing clock frequencies, power consumption of hardware designs has become a critical metric (besides area and latency) that should be taken into consideration while evaluating the viability and success of a synthesis process. In this work, we analyze the complexity of low-power problems associated with the action-oriented specification models, and propose algorithms and techniques for power optimization during the action-oriented synthesis process. Furthermore, verification of hardware designs generated from such models is required in order to verify the changes caused in their structures or behaviors as part of any used power minimization techniques. Verification of high-level action-oriented models is also important for ensuring the correctness of the designs early in the design cycle. In this work, we also propose various formal verification techniques that can be used for verifying desired correctness properties as well as behaviors of power-minimized action-oriented designs at high-level. / Ph. D.

Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power dissipated during functional mode operation, the test mode average power may sometimes go upto 3x and the peak power may sometimes go upto 30x of normal mode operation. The power dissipated during the scan operation is primarily due to the switching activity that arises in scan cells during the shift and capture operation. The switching in scan cells propagates to the combinational block of the circuit during scan operation, which in turn creates many transition in the circuit and hence it causes higher dynamic power dissipation. The excessive average power dissipated during scan operation causes circuit damage due to higher temperature and the excessive peak power causes yield loss due to IR-drop and cross talk. The higher peak power also causes the thermal related issue if it last for sufficiently large number of cycles. Hence, to avoid all these issues it is very important to reduce the peak power during scan testing. Further, in case of multi-module SoC testing the reduction in peak power facilitates in reducing the test application time by scheduling many test sessions parallelly. In this dissertation we have addressed all the above stated issues. We have proposed three different techniques to deal with the excessive peak power dissipation problem during test. The first solution proposes an efficient graph theoretic methodology for test vector reordering to achieve minimum peak power supported by the given test vector set. Three graph theoretic problems are formulated and corresponding algorithms to solve the problems are proposed. The proposed methodology also minimizes average power for the given minimum peak power. Further, a lower bound on minimum achievable peak power for a given test set is defined. The results on several benchmarks show that the proposed methodology is able to reduce peak power significantly. To address the peak power problem during scan test-cycle (the cycle between launch and capture pulse) we have proposed a scan chain reordering technique. A new formulation for scan chain reordering as TSP (Traveling Sales Person) problem and a solution is proposed. The experimental results show that the proposed methodology is able to minimize considerable amount of peak power compared to the earlier proposals. The capture power (power dissipated during capture cycle) problem in testing multi chip module (MCM) is also addressed. We have proposed a methodology to schedule the test set to reduce capture power. The scheduling algorithm consist of reordering of test vector and insertion of idle cycle to prevent capture cycle coincidence of scheduled cores. The experimental results show the significant reduction in capture power without increase in test application time.

Clock scheduling is studied to improve the performance of synchronous sequential circuits. The performance improvement covers the optimization of the clock frequency and the peak power consumption, separately. For clock period minimization, cycle stealing method is utilized, in which the redundant cycle time of fast combinational logic is transferred to slower logic by proper clock skew adjustment of registers. The clock scheduling system determines the minimum clock period that a synchronous sequential circuit can operate without hazards. The timing of each register is adjusted for operation with the minimum clock period. The dependence of the propagation delays of combinational gates on load capacitance values are modeled in order to increase the accuracy of the clock period minimization algorithm. Simulation results show up to 45% speed-up for circuits that are scheduled by the system. For peak power minimization, the dependence of the switching currents of circuit elements on the load capacitance values are modeled. A new method, namely the Shaped Pulse Approximation Method (SPA), is proposed for the estimation of switching power dissipation of circuit elements for arbitrary capacitive loads. The switching current waves can accurately be estimated by using the SPA method with less than 10% normalized rms error. The clock scheduling algorithm of Takahashi for the reduction of the peak power consumption of synchronous sequential circuits is implemented using the SPA method. Up to 73% decrease in peak power dissipation is observed in simulation results when proper clock scheduling scheme is applied to test circuits.

The unique environment of CubeSat and small satellite missions allows certain accepted paradigms of the larger satellite world to be investigated in order to trade performance for simplicity, mass, and volume. Peak Power Tracking technologies for solar arrays are generally implemented in order to meet the End-of-Life power requirements for satellite missions given radiation degradation over time. The short lifetime of the generic satellite mission removes the need to compensate for this degradation. While Peak Power Tracking implementations can give increased power by taking advantage and compensating for the temperature cycles that solar cells experience, this comes at the expense of system complexity and, given smart system design, this increased performance is negligible and possibly detrimental. This thesis investigates different Peak Power Tracking implementations and compares them to two Fixed Point implementations as well as a Direct Energy Transfer system in terms of performance and system complexity using computer simulation. This work demonstrates that, though Peak Power Tracking systems work as designed, under most circumstances Direct Energy Transfer systems should be used in small satellite applications as it gives the same or better performance with less complexity.

The purpose of this study was to examine changes in muscle architecture and jumping performance in NCAA division I women's volleyball players throughout a competitive season and in preparation for conference championships. Ten women volleyball players were tested at preseason (T1), pretaper (T2), and post-taper (T3) on measures of vastus lateralis muscle thickness (MT), pennation angle (PA) and fascicle length (FL) using ultrasonography, and unloaded and loaded squat jump height (SJH) and peak power allometrically scaled to body mass (SJPPa) on a force platform. Rating of perceived exertion training load and strength training volume load were monitored weekly. Player's MT (p < 0.001, Glass's Δ = 2.8) and PA increased (p = 0.02, Δ = 3.9) after in-season training. However, MT decreased after the taper (p = 0.01, Δ = 0.6) but remained elevated above preseason values (p < 0.001, Δ = 1.7). There were no statistical changes in FL, SJH, or SJPPa. Large-to-very large negative relationships (r = −0.51 to −0.81) were observed between preseason relative maximal strength and changes in SJH and SJPPa with various loads over the season. These findings demonstrate that relatively low volumes of strength training and concurrent sport training during a tapering period are capable of preserving jumping performance, but not MT in women's volleyball players; however, jumping performance changes seem to be related to the player's strength level. Stronger players may benefit from an overreaching microcycle before the taper to preserve previously accrued muscular adaptations and jumping performance.

We determined whether aging diminishes bone blood flow and impairs endothelium‐dependent vasodilation. Femoral perfusion was lower in old animals, as well as endothelium‐dependent vasodilation and NO bioavailability. These effects could contribute to old age—related bone loss and the increased risk of fracture. Introduction: Aging has been shown to diminish bone blood flow in rats and humans. The purpose of this study was to determine whether blood flow to regions of the femur perfused primarily through the principal nutrient artery (PNA) are diminished with aging and whether this putative reduction in flow is associated with impaired endothelium‐dependent vasodilation. Materials and Methods: Blood flow was measured in conscious young adult (4–6 mo old) and aged (24–26 mo old) male Fischer‐344 rats using radiolabeled microspheres. Endothelium‐dependent vasodilation of the PNA was assessed in vitro using acetylcholine (ACh), whereas the contribution of the NO synthase (NOS) and cyclooxygenase (COX) signaling pathways to endothelium‐dependent vasodilation was determined using the NOS and COX inhibitors L‐NAME and indomethacin, respectively. Results: Femoral blood flow in the aged rats was 21% and 28% lower in the proximal and distal metaphyses, respectively, and 45% lower in the diaphyseal marrow. Endothelium‐dependent vasodilation was reduced with old age (young: 83 ± 6% maximal relaxation; aged: 62 ± 5% maximal relaxation), whereas endothelium‐independent vasodilation (sodium nitroprusside) was unaffected by age. The reduction in endothelium‐dependent vasodilation was mediated through impairment of the NOS signaling pathway, which resulted in lower NO bioavailability (young: 168 ± 56 nM; aged: 50 ± 7 nM). Conclusions: These data show that reductions in metaphyseal bone and diaphyseal marrow perfusion with old age are associated with diminished endothelium‐dependent vasodilation through an impairment of the NOS mechanism. Such age‐related changes in bone perfusion and vascular NO signaling could impact clinical bone loss, increase risk of fracture, and impair fracture healing in the elderly.