With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

A conventional RF power amplifier will convert the low powered radio frequency signals into high powered signals. Along with the expected ability to increase the communication distance, data transfer rates, RF power amplifiers also have many applications which include military radar system, whether forecasting, etc. The main objective of any power amplifier research is to increase the efficiency while maintaining linearity and broadening the frequency of operation. The main motivation for the renewed interest in PA technology comes from the technical challenges and the economics of modern digital communication systems. Modern communications require high linear power amplifiers and in order to reduce the complete system cost, it is necessary to have a single broadband power amplifier, which can amplify multiple carriers. The improvement in the efficiency of the power amplifier increases the battery life and also reduces the cooling requirements for the same output power. In this thesis, I aim to design and build a wideband class J power amplifier suitable for modern communications. For wideband operation of the GaN technology PA, a bandwidth extension design method is studied and implemented. The simulation results are proved to have a good argument with the theoretical calculations.

The interest in higher data rate systems is rising very quickly in the area of wireless communications. High data rates mean high Peak to Average Ratio, PAR. This imposes big challenge on the linearity requirement of Power Amplifiers, PAs. The simplest technique that has been used is backing off the PA. However, this leads to very inefficient performance. A lot of more complex techniques were suggested in the literatures to trick the tradeoff between linearity and efficiency. So we discuss the advantages and disadvantages of those techniques. In addition we suggest a new technique called Power Amplifier Linearization using a Mirror Predistorter. This technique is based on the use of a mirror PA that generates a copy of the main PA nonlinearity, and then feeds it in the proper phase and magnitude into the input in order to cancel the intermodulation terms at the output. Simulation and on the bench lab results validate the suggested technique. Also a hybrid PA module was designed and tested based on the suggested technique, and showed an improvement of 23 dB in the Third Order Intermodulation to Carrier ratio, IMD3 of the PA at 7.5 dB back off. / Master of Science

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Even though there had been extensive research in Switching Mode Power Amplifier design their applications at industry level are quite limited. This is because a Fully-Integrated Switching Mode Power Amplifier using conventional active devices such as Bipolar Junction Transistors (BJT) or Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is challenging due to the inherent design challenges in the Switching Power Amplifier design. A Fully-Integrated Differential Class-F2,3 Power Amplifier design is explored for this Thesis research. This Power Amplifier has a maximum theoretical efficiency of 90.7% but this value is reduced because of the switching nature of the active device, parasitic effects associated with layout and the quality factor of the passive components used. Waveform shaping required for a Class-F Power Amplifier is done using the stray inductances within a non-ideal transformer instead of individual inductors. This techniques effective reduces the foot prints of two inductors for the tuning network design and make a Fully-Integrated solution more practical.

This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS. / Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.

The rapid evolution of wireless communication technologies increased the need for handheld devices that can support dissimilar standards or better user mobility and more battery life. Traditional radio architectures fail to satisfy these challenging features. Software Defined Radio (SDR) is recently introduced to implement a new generation of wireless radios capable of coping with these stringent requirements through software reprogramming. Although the term SDR is widely used, it is still an idealized method and is not implementable using available technologies. Hence, the term “SDR”, has been so far, referring to only partially upgradeable radios. Two current practical solutions substituting SDR are broadband and multiband transceivers. Radio Frequency (RF) front ends and especially the power amplifier is the main challenge in implementation of software defined radios. Power Amplifiers (PA) dominate the sources of distortions and power consumption in the RF-front end. They are typically operated in linear classes in order to minimize the linearity degradation. However, they lead to poor average power efficiency especially when fed with signals with high Peak to average power ratio (PAPR) such as Wideband Code Division Multiple Access (W-CDMA) and Long Term Evolution (LTE) signals. This is the main cause of short battery life in transceivers. To remedy this issue, some advanced methods like Doherty amplifier and drain modulation based architectures are introduced. This thesis expounds on the implementation of high efficiency radio transmitters, capable of multi standard operation. The RF amplifier is still one of the main challenges in the realization of these transmitters. In this work, two RF PAs, having multiband and broad band characteristics, were implemented using 0.13µm CMOS technology. The first PA operates at two frequency bands, 2.4GHz and 3.5GHz. The other PA has center frequency equal to 2.4GHz and 600MHz bandwidth, respectively. These PAs are expected to lay the foundation for the realization of high efficiency drain modulation based multiband and broadband transmitters.

The rapid evolution of wireless communication technologies increased the need for handheld devices that can support dissimilar standards or better user mobility and more battery life. Traditional radio architectures fail to satisfy these challenging features. Software Defined Radio (SDR) is recently introduced to implement a new generation of wireless radios capable of coping with these stringent requirements through software reprogramming. Although the term SDR is widely used, it is still an idealized method and is not implementable using available technologies. Hence, the term “SDR”, has been so far, referring to only partially upgradeable radios. Two current practical solutions substituting SDR are broadband and multiband transceivers. Radio Frequency (RF) front ends and especially the power amplifier is the main challenge in implementation of software defined radios. Power Amplifiers (PA) dominate the sources of distortions and power consumption in the RF-front end. They are typically operated in linear classes in order to minimize the linearity degradation. However, they lead to poor average power efficiency especially when fed with signals with high Peak to average power ratio (PAPR) such as Wideband Code Division Multiple Access (W-CDMA) and Long Term Evolution (LTE) signals. This is the main cause of short battery life in transceivers. To remedy this issue, some advanced methods like Doherty amplifier and drain modulation based architectures are introduced. This thesis expounds on the implementation of high efficiency radio transmitters, capable of multi standard operation. The RF amplifier is still one of the main challenges in the realization of these transmitters. In this work, two RF PAs, having multiband and broad band characteristics, were implemented using 0.13µm CMOS technology. The first PA operates at two frequency bands, 2.4GHz and 3.5GHz. The other PA has center frequency equal to 2.4GHz and 600MHz bandwidth, respectively. These PAs are expected to lay the foundation for the realization of high efficiency drain modulation based multiband and broadband transmitters.

This thesis consists of two parts. Part one presents a design of class-AB power amplifier in 0.15£gm pHEMT process, and establishes a nonlinear model with memory effects for the power amplifier using Volterra series. To observe the memory effects, two-tone continuous wave signals have been applied to the model to predict the phase variation between IM3H and IM3L as a function of tone spacing. In the meanwhile, a time-domain measurement technique for the third-order intermodulation responses using a digital storage oscilloscope has been developed to verify the modeled predictions on IM3H and IM3L. Comparison between modeled and measured results shows good agreement. Part two of this thesis is to study the CMOS power-combining techniques. At first, the pros and cons between series and parallel combining transformers are discussed. Then, a design of class-E power amplifier using a pair of parallel combining transformers for power combining is presented. Both simulated and measured results show that the presented Class-E power amplifier has a high power-added efficiency.

Abstract¡G This thesis was consisted of two parts. Part 1 introduced the procedure for designing the RF transceiver module in an IS-95 CDMA system using link budget analysis. Part 2 was focused on a CDMA power amplifier integrated circuit design for Personal Communication Service (PCS) applications. The design procedure was introduced in detail and implemented in MMIC for using GaAs HBT foundry provided by the GCS Ltd.. The designed linear gain, output 1dB compression point and power added efficiency (PAE) are above 30 dB, 27 dBm and 36.7% respectively under a single supply voltage of 3.4 V with the help of a diode linearizer. Harmonic components were suppressed more than 26 dB without use of any filters in the output. The adjacent channel power ratio (ACPR) and the VSWR of input port are below -45 dBc and 2 respectively.