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With the rapid expansion of wireless communication services, ultra-miniature, low cost RF microsystems operating at higher carrier frequencies (e.g. 5-6 GHz) are in demand for various applications. Such applications include networked wireless sensor nodes and wireless local area data networks (WLANs). Integrated microstrip antennas coupled directly to the RF electronics, offer potential advantages of low cost, reduced parasitics, simplified assembly and design flexibility compared to systems based on discrete antennas. However, the size of such antennas is governed by physical laws, and cannot be arbitrarily reduced. The critical patch antenna dimension at resonance needs to be ~ λ_g/2 (where λ_g is the guided wavelength given by λ_g=λ₀/√(𝜖_r) . Several methods are available to reduce the physical size of the antenna to enable on-chip integration. A high dielectric constant substrate reduces the guided wavelength. Grounding one edge of the microstrip patch enables the resonant antenna length to be further reduced to ~ λ_g/4. However, these techniques result in degraded antenna efficiency and bandwidth. Nonetheless, such antennas still have potential for use in low power/short range applications. In this work, "electrically small" (small with respect to λ₀) square-shaped microstrip patch antennas, grounded on one edge by shorting posts, have been investigated. The antenna input impedance depends on the feed position; by adjusting the feed point, the antenna can be tuned to match a 50 Ω or other system impedance. The antennas were designed on a GaAs substrate, with a high dielectric constant of 12.9. The size of the patch antenna is further reduced by utilizing shorted through substrate vias along one edge. The size of the antenna is about 4.2mm × 4.2mm, which is ~1/13 of λ₀ at ~5.6GHz. The antennas are practical for integration on chip. Due to the size reduction, the simulated peak gain of the antenna is only −10.2 dB (~3.2% radiation efficiency). However, this may be acceptable for short-range wireless communications and distributed sensor network applications. Based on the above approach, integrated GaAs "chip-scale" antennas with matching power amplifiers have been designed and fabricated. Class A tuned MESFET power amplifiers (PAs) were designed with outputs directly matched to the antenna feed point. The antenna is fabricated on the backside of the chip through backside patterning; the PA feeds the antenna through a backside via. The structure is then mounted such that the antenna faces up, and is compatible with flip-chip technology. The measurement of a 50 Ω passive (no PA) antenna indicates a gain of -12.7dB on boresight at 5.64 GHz, consistent with the antenna size reduction. The measurement of one active antenna (50 Ω system) shows a gain of -4.3dB on boresight at 5.80 GHz. The other version of active antenna (22.5 Ω system) shows a gain of −2.9 dBi on boresight at 5.725 GHz. The active circuitry (PA) contributes an average of ~9 dB gain in the active antenna, reasonable close to the designed PA gain of 12.7dB. The feasibility of direct integration of a PA with an on-chip antenna in a commercial GaAs process at RF frequencies was successfully demonstrated. / Master of Science

Cellular radio communication involves wireless transmission and reception of signals at radio frequencies (RF). Base stations house equipment critical to the transmission and reception of signals. Power amplifier (PA) is a crucial element in base station assembly. PAs are expensive, take up space and dissipate heat. Of all the elements in the base station, it is difficult to design and operate a power amplifier. New designs of power amplifiers are constantly tested. One of the most important components required to perform this test successfully is a circuit simulator model of an entire communication system that generates a standard test signal. Standard test signals 524,288 data points in length require 1080 hours to complete one test of a PA model. In order to reduce the time taken to complete one test, a 'simulated test signal,' was generated. The objective of this study is to develop an algorithm to generate this 'simulated' test signal such that its characteristics match that of the 'standard' test signal.

Linearity and efficiency are both critical parameters for radio frequency transmitter applications. In theory, a Doherty amplifier is a linear amplifier that is significantly more efficient than comparable conventional linear amplifiers. It comprises two amplifiers, connected at their outputs by a quarter-wave transformer. The main amplifier is always on, while the peaking amplifier is off during low power levels. Load modulation of the main amplifier occurs when the peaking amplifier is on due to the quarter-wave transformer, ensuring the main amplifier never enters saturation. This results in an efficiency characteristic that increases with respect to input power at twice the normal rate at low power levels, and plateaus to a high value at high power levels. However, in much of the research that has been done to-date, less-than-ideal results have been achieved (although efficiency was better than a conventional amplifier). It was decided to investigate the cause of the discrepancy between theoretical and practical results, and devise a method to counteract the problem. It was discovered that the main cause of the discrepancy was non-ideal transistor gate-voltage to drain-current characteristics. The implementation of a gate bias control scheme based upon measured transistor transfer characteristics, and the desired main and peaking amplifier output currents, resulted in a robust method to ensure near-ideal results. A prototype amplifier was constructed to test the control scheme, and theoretical, simulated and measured results were well matched. The amplifier had a region of high efficiency in the high power levels (over 34% for the last 6 dB of input power), and the gain was nearly constant with respect to input power (between 4 and 5 dB over the dynamic range). Furthermore, it was decided to investigate the role harmonics play within the Doherty amplifier. A classical implementation shunts unwanted harmonics to ground within the main and peaking amplifiers. However, odd harmonics generated by the peaking amplifier can be used to operate the main amplifier like a class F amplifier. This means its supply voltage can be lowered, without the amplifier entering saturation, and the efficiency of the Doherty amplifier can be increased without a detrimental effect on the its linearity. A prototype amplifier was constructed to test this theory, and gave good results, with better efficiency than that of a conventional amplifier, and a constant gain with respect to input power (between 6.4 dB and 6.5 dB over the dynamic range).

With the ongoing push for wireless systems to accommodate more users and support higher data rates more efficient modulation schemes have been created that are more advanced than simple FM and AM modulation used for radio broadcasting. These modulation schemes, such as orthogonal frequency division multiplexing (OFDM), suffer from high peak to average power ratios. Standard Class A and Class AB amplifiers cannot simultaneously achieve good linearity and efficiency, and therefore there has been an increase in the development of new topologies to combat this issue. Common features to these circuits is power combining of two or more separate transistors. In this work, we consider various ways of two-source power combining and identify four topologies of interest. We notice that linear power-efficient amplifiers reported to date are based upon two of the identified combining strategies. We believe that no amplifiers have been reported that leverage the other two alternatives. This work produces a fully-functional amplifier based on one of these alternatives. The prototypes are intended to serve as concept verification of the architecture and hence are implemented at lower (1 MHz) frequencies.

This master’s thesis describes RF power amplifier design. The designed amplifier has been built. The first three chapters outline basics about radio frequency amplifiers. The basic theory needed for amplifier implementation is also described there. In the fourth chapter the power amplifier is designed. The design is based on the theoretical knowledge. Complete amplifier contains RF preamplifier, power amplifier and filters. The OrCAD PSpice, Ansoft Designer SV and EAGLE programs have been used for the design and verification of some sections of circuits. Measurement results of the built amplifier are in the fifth chapter. This thesis contains also the draft for laboratory exercise.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / M/A-COM has developed a chip set designed specifically for miniaturized ballistic telemetry applications. One key component of this chip set is a dual port voltage controlled oscillator (VCO). This device allows for independent optimization of both modulation and tuning parameters at the chip level. In the dual port architecture, the modulation port of the VCO may be tailored for the peak (frequency) deviation requirements of each system, while still permitting the device to tune over entire SLOWER band. Additionally, M/A-COM has developed S band power amplifiers (PAs) for medium power (500mW, 1W and 2W) telemetry applications. These new PAs are very efficient, (>45% PAE) when operated in saturation. This improved efficiency means these components may be integrated into transmitters with a miniaturized form factor. The excellent thermal performance of these new PAs allows them to be packaged in commercial plastic packages which are robust in high shock/high vibration applications. This paper reviews the design of each MMIC device and presents system performance data.

Doctor of Philosophy / Department of Electrical and Computer Engineering / William B. Kuhn / Design challenges and solution methods for Watt-level UHF CMOS power amplifiers are presented. Using the methods, a fully-integrated UHF (400MHz) CMOS power amplifier (PA) with more than 1-Watt output is demonstrated for the first time in Silicon on Sapphire (SOS) process. The design techniques are extended for a two-stage five-chip 5-Watt CMOS PA. In the 1-Watt PA, a differential stacked PMOS structure with floating-bias and a 1:3 turns-ratio output transformer are chosen to overcome low breakdown voltage (Vbk) of CMOS and chip area consumption issues at UHF frequencies. The high Q on-chip transformer on sapphire substrate enables the differential PA to drive a single-ended antenna effectively at 400 MHz. The PA is designed for a surface-to-orbit proximity link microtransceiver, used on Mars exploration rovers, aerobots and small networked landers. In a standard package the PA delivers 30 dBm output with 27 % PAE. No performance degradation was observed in continuous wave (CW) operation with various output terminations and the PA was tested to 136 % of its nominal 3.3 V supply without failure. Stability analysis and measurements show that the PA is stable in normal operation. It is also shown that the PA is thermally reliable. In the microtransceiver circuits, the PA works in conjunction with transmit/receive (TR) switch to allow nearly the full 1-Watt to reach the antenna. The 1-Watt PA design is also leveraged to demonstrate a power-combined two-stage five-chip PA. The 1-Watt PA’s output balun is modified for the four-transformer combining. Four identical chips are wire-bonded in the output stage and the fifth identical chip is added as a drive-amplifier. Despite low efficiency due to damaged bias circuits, the PA provides 5-Watt output power (37 dBm) at 480 MHz with 17 % PAE with 17 dB gain. The PA layout is carried out considering full integration on a 7×10mm2 die. It will be the highest output CMOS PA ever reported once the full integration is implemented. The research contributes to state of the art by developing design-techniques for a TR switch and PAs on SOS process. The resonant TR switch technique is applied to a full transceiver and the multi turns-ratio on-chip transformer is used in PA’s output matching network for the first time. The PA design is also extended to the 5-Watt PA, demonstrating the highest output power in CMOS process.

Master of Science / Department of Physics / Brian R. Washburn / Rare-earth doped optical fibers can be used to make optical amplifiers in the near infrared with large optical gain in an all fiber based system. Indeed, erbium doped fibers made gain possible within the 1532 to 1560 nm band which makes long span fiber optical communication systems a possibility. Erbium doped fibers have also been used to make narrow linewidth or mode-locked lasers. Other rare-earth doped fibers can be used for amplifiers in other near-infrared spectral regions. Recently, fiber amplifier technology has been pushed to produce watt level outputs for high power applications such as laser machining. These high power amplifiers make new experiments in ultrafast fiber optics a possibility. This report reviews the current literature on Watt-class continuous wave erbium doped amplifiers and discussed our attempt to develop a high power Yb/Er amplifier. After the design of the cladding pump in 1999, the world’s first single mode fiber laser with a power greater than 100 Watts of the continuous wave light was introduced. After 2002 there was a huge spike in the output powers (up to 2 kW) of lasers based on rare-earth doped fibers. Our own work involved developing a 10 W amplifier at 1532 nm and 1560 nm. A high power amplifier was made by seeding a dual-clad Yb/Er co-doped fiber pumped at 925 nm using a lower power erbium doped fiber amplifier. We will discuss the design and construction of the amplifier, including the technical difficulties for making such an amplifier.