This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe. Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier. The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power. A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network. Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers. / Ph. D.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

This research work has made an effort to understand a novel line of radio frequency power amplifiers (RFPAs) that address initiatives for efficiency enhancement and linearity compensation to harmonize the fifth generation (5G) campaign. The objective is to enhance the performance of an orthogonal frequency division multiplexing-long term evolution (OFDM-LTE) transmitter by reducing the nonlinear distortion of the RFPA. The first part of this work explores the design and implementation of 15.5 W class AB RF power amplifier, adopting a balanced technique to stimulate efficiency enhancement and redeeming exhibition of excessive power in the transmitter. Consequently, this work goes beyond improving efficiency over a linear RF power amplifier design; in which a comprehensive investigation on the fundamental and harmonic components of class F RF power amplifier using a load-pull approach to realise an optimum load impedance and the matching network is presented. The frequency bandwidth for both amplifiers was allocated to operate in the 2.620-2.690 GHz of mobile LTE applications. The second part explores the development of the behavioural model for the class AB power amplifier. A particular novel, Hammerstein-Wiener based model is proposed to describe the dynamic nonlinear behaviour of the power amplifier. The RF power amplifier nonlinear distortion is approximated using a new linear parameter approximation approach. The first and second-order Hammerstein-Wiener using the Normalised Least Mean Square Error (NLMSE) algorithm is used with the aim of easing the complexity of filtering process during linear memory cancellation. Moreover, an enhanced adaptive Wiener model is proposed to explore the nonlinear memory effect in the system. The proposed approach is able to balance between convergence speed and high-level accuracy when compared with behavioural modelling algorithms that are more complex in computation. Finally, the adaptive predistorter technique is implemented and verified in the OFDM transceiver test-bed. The results were compared against the computed one from MATLAB simulation for OFDM and 5G modulation transmitters. The results have confirmed the reliability of the model and the effectiveness of the proposed predistorter. / Fundacão para a Ciência e a Tecnologia, Portugal, under European Union’s Horizon 2020 research and innovation programme ... grant agreement H2020-MSCA-ITN- 2016 SECRET-722424 I also acknowledge the role of the National Space Research and Development Agency (NASRDA) Sokoto State Government Petroleum Technology Trust Fund (PTDF)

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / M/A-COM, Inc. has developed a miniature Tactical Telemetry Module (TTM) for medium power (500 mW and 1 W) telemetry applications. The TTM demonstrates system integration of a multi-channel PCM encoder, lower S-band transmitter, and power regulation onto a single printed wiring board (PWB). The module is smaller than a standard business card and utilizes both COTS and M/A-COM proprietary technologies. The PCM encoder is designed for eight (8) analog inputs, eight (8) discrete inputs, and one (1) synchronous RS-422 serial interface. Data rates of 300 kbps to 6 Mbps are supported. The module incorporates a frequency programmable, phase-locked FM S-band transmitter. The transmitter utilizes M/A-COM’s new dual port VCO and high efficiency 500 mW and 1 W power amplifier MMIC’s. Additionally, switching power regulation circuits were implemented within the module to provide maximum operating efficiency. This paper reviews the design and manufacturing of the Tactical Telemetry Module (TTM) and its major components, and presents system performance data.

ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / A study of the effects of interference caused by adjacent channels on the performance of turbo-coded 16- and 32-APSK. Included in our discussion is the spectral regrowth in the nonlinear power amplifier when driven by a non-constant envelope modulation. Ultimately, we present a set of channel spacing guidelines when using turbo-coded APSK for aeronautical telemetry.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / A miniature 1 Watt Tactical Telemetry Module (TTM) has been developed for the Excalibur projectile program. The TTM incorporates a multi-channel PCM encoder, lower S-band transmitter, and power regulation onto a single printed wiring board (PWB). The PCM encoder is designed for eight (8) analog inputs, four (4) discrete inputs, and one (1) synchronous RS-422 serial interface, with a total data rate of 1 Mbps. The module incorporates a digitally programmable, phase-locked FM S-band transmitter. The transmitter utilizes M/A-COM’s new dual port VCO and a high efficiency 2 W power amplifier MMIC. Additionally, switching power regulation circuits were implemented within the module to provide maximum operating efficiency. This paper reviews the environmental requirements of Excalibur, the design of the Excalibur TTM, and presents electrical and air-gun test data.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / M/A-COM, Inc. has previously developed a highly integrated transmitter chip set for wireless telemetry applications for the military L and S band frequencies and the commercial 2.4GHz ISM band. The original chip set is comprised of a voltage controlled oscillator (VCO), a silicon phase locked loop (PLL), and a family of power amplifiers (PA's). Using these components, M/A-COM has produced a miniature IRIG-compliant transmitter module, which has been flight-tested by the U.S. Army’s Hardened Subminiature Telemetry and Sensor System (HSTSS) program. Since the initial offering, several product enhancements have been added. The module performance has been improved by tailoring the VCO specifically for direct frequency modulation applications. In addition to improving noise performance, these enhancements have produced improved modulation linearity, decreased lock time and increased carrier stability. Modulation rates in excess of 10Mbps have been demonstrated. High efficiency power amplifiers operating at 3V have also been added to the family of amplifiers (PAE > 50%). This greatly enhanced efficiency allows higher RF power output while maintaining the same miniature form factor for the transmitter. Further, M/A-COM has added a silicon-on-sapphire PLL to the chip set, which operates at frequencies up to 3.0GHz. This paper details the enhancements to the components within the chip set, and the improvement in performance of the transmitter module. Test data is presented for the transmitter modules and individual components.

Le standard LTE permet l’accès au très haut débit mobile et évolue afind’adresser les applications embarquées de type objets connectés. Mais dans la perspectived’un émetteur-récepteur LTE fabriqué dans une technologie CMOS faible-coût ethautement intégrable, l’amplificateur de puissance (PA) reste le seul bloc actif non intégréà ce jour. De plus, l’utilisation de modulations en quadrature oblige la conceptiond’amplificateurs très linéaires, générant une consommation statique plus importante.Dans ce contexte, ces travaux de thèse portent sur la recherche de composants etde circuits permettant d’atteindre de fortes puissances de sortie et de résoudre le compromisentre la linéarité et la consommation du PA. Deux axes de travail sont identifiéset développés dans cette thèse. Le premier axe porte sur l’utilisation d’un transistor depuissance intégrable en technologie CMOS. Trois cellules de puissance basées sur ce composantsont présentées, de l’étude théorique aux résultats de mesure. Dans le second axede recherche, ce transistor est intégré dans une architecture avancée de PA entièrementréalisée en CMOS. Une méthode de conception de transformateurs intégrés est égalementdéveloppée. Le PA proposé est reconfigurable pour adresser les différents besoinsimposés par le standard LTE : puissance de sortie, haute linéarité et faible consommation. / The LTE standard has been intended for mobile communications. Focusingnot only on higher data rate, LTE now aims at an implementation for the Internetof Things (IoT). The main challenge, in the perspective of a LTE front-end fully manufacturedin a low-cost and high integration level CMOS technology, remains the design ofpower amplifiers (PA). Furthermore, the use of complex quadrature modulation resultsin stringent linearity requirements resulting in an important quiescent dc consumption.In this context, this work focuses on the research of devices and circuits generatinghigh output power and solving the compromise between linearity and consumption ofthe PA. Two strands of work are identified and developed in this thesis. The first oneuses a power transistor available in CMOS technology. Three power cells based on thisdevice are proposed, with detailed theoretical and experimental results. In the secondone, this transistor is then used in a fully-integrated CMOS PA. A design methodologyfor integrated transformers is also presented. The proposed fully-integrated PA is reconfigurablein order to address the main LTE challenges : output power, high linearity andlow consumption.

Comme toutes modulations multiporteuses, l'OFDM souffre d'une forte variation d'amplitudes qui se traduit par un PAPR élevé. Cette caractéristique de l'OFDM la rend très sensible aux non-linéarités de l'amplificateur de puissance. Pour faire face à cette problématique, on peut surdimensionner l'amplificateur de puissance (solution non efficace en terme de rendement énergétique), linéariser l'amplificateur via les techniques de pré-distorsions, ou réduire le PAPR du signal avant amplification. L'objectif de cette thèse s'inscrit dans cette dernière thématique et plus particulièrement sur les techniques dites d'ajout de signal.Dans cette thèse, après une étude sur l'état de l'art des techniques de réduction du PAPR et en particulier les techniques dites d'ajout de signal, nous avons développé et proposé de nouvelles techniques de réduction du PAPR. Ces contributions s'articulent principalement autour des techniques de Clipping et de la Tone Reservation. / One of the main drawbacks of the OFDM modulation scheme is its high Peak-To-Average Power variation (PAPR) which can induce poor power efficiency at the transmitter amplifier. The digital base band pre-distortion for linearisation of power amplifier and the PAPR mitigation are the most commonly used solution in order to deals with efficiency and linearisation at the high power amplifier. This thesis is focused on the PAPR mitigation solution, and particularly on the adding signal based techniques. The proposed solutions in this report are about improving the Tone Reservation method which is the most popular adding signal based technique for PAPR mitigation, and also the classical clipping method which is the most simple method (in terms of computational complexity) actually.