abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

<p>This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using LDMOS technologies. It involves a literature study of different SMPA concepts. Choosing the suitable class that achieves the high efficiency was the base stone of this</p><p>work. A push-pull class J power amplifier (PA) was designed with an integrated LC resonator inside the package using the bondwires and die capacitances. Analysis and motivation of the chosen class is included. Designing the suitable Input/Output printed circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC</p><p>bias network) was part of the work. This work is done by ADS simulation and showed a simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at 2.14 GHz. Study of the losses in each part of the design elements is also included.</p><p>Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB Gain.</p>

This thesis aims to use a hybrid quadrature polar modulator (HQPM) for enhancing average efficiency of 3G mobile transmitter with power control. The HQPM consists of a quadrature modulator instead of a phase modulator in the polar modulator for processing the RF modulated carrier and a Class-S modulator for processing the envelope signal. In addition, the instantaneous magnitude of the quadrature modulated signal is propotional to the instantaneous envelope magnitude. As a result, the output feed-through and gain-compression phenomenon in the polar modulator can be improved. The digital baseband processor realized by FPGA can generate CDMA2000 1x baseband signal with excellent modulation accuracy. For enhancing the average transmit efficiency, the output PA is realized as Class-E design. But the Vdd/AM and Vdd/PM nonlinear effects of the Class-E PA distort the output signal. To solve this problem, a digital predistorter is presented to compensate the nonlinear distortions. The proposed HQPM-based transmitter can simultaneously achieve high efficiency and high linearity over a wide modulated output power range.

The trade-off between linearity and efficiency is the key limiting factor to wideband power amplifier design. Current wireless research focuses much of its effort on building power amplifiers with the two aforementioned criteria going hand in hand to build an optimal design. This thesis investigates the sources of nonlinearity associated with GaN high electron mobility transistors (HEMT), and their subsequent effects on the linearity metrics of the power amplifier. The investigation began with an analysis of the sources of nonlinearity, and then a design-based approach to mitigate those sources of nonlinearity was developed. This design approach was compared with existing trends in power amplifier design. The device technology used in the design was CREE GaN HEMT (45W and 6W). In this report, a systematic approach to designing a two stage power amplifier is discussed, and analyzed for design of linear and highly efficient power amplifiers for base stations. The designed power amplifier consists of two stages: a driver stage and a power stage. The driver stage aimed to linearize the power stage by using circuit analysis and transistor properties along with providing the necessary gain. The power stage was built to complement the driver stage and to achieve high efficiency for the power amplifier. An inter-stage matching network placed between the two stages allowed for the required matching of impedances; transmission lines in the bias feed controlled the harmonic impedances for optimal performance without disrupting performance at fundamental frequencies. This approach effectively improved, and maintained, high efficiency over 200MHz of bandwidth. The design approach was simulated and fabricated in order to test the feasibility of linear power amplifier operation with the use of digital pre-distortion (DPD). The fabricated prototype achieved about 70% peak efficiency over the bandwidth and maintained linearity above 40dBc adjacent channel leakage ratio (ACLR) and below 3% error vector magnitude (EVM). The measurement results indicated that the need for DPD was eliminated when the power amplifier was operating in back-off at the center frequency (800MHz). This thesis compares the prototyped design with existing multistage designs which use linear drivers. The report provides conclusions derive from measurement results and bandwidth limitations faced throughout the course of the design. Lastly, potential research directions, which may allow researchers to overcome the limitations of this design, are discussed.

This thesis starts with a discussion of different classes of operation of power amplifiers (PAs). Comparing advantages and disadvantages of these classes, class AB is chosen as the best initial candidate for the design of broadband PA. Different methods for design of matching networks are first discussed. Some of them fall into the group of narrowband matching networks, while others are suitable for a broadband context. Broadband design methodologies are categorized into two groups of real-to-real transformations and complex-to-real transformations. Complex-to-real transformations are the most useful methods for this project, since design of power amplifiers deals with complex loads rather than just real loads. The design of broadband matching networks exploiting filter theory is presented in this thesis for synthesizing broadband and highly efficient power amplifiers (PAs). Starting with sets of optimum impedances over the targeted frequency band, the matching networks are designed using a systematic approach. The effects of load termination at the 2nd and 3rd harmonic on the PA performance (efficiency) are studied. The significance of proper termination, especially at the 2nd harmonic, is highlighted. To prevent further complication of the design process, though, specific harmonic termination (stubs) is avoided and special arrangement of the matching network (position of the bias network) is preferred, as it is found to lead to acceptable efficiency. Two PA prototypes were designed with the proposed methodology using 25W GaN devices. The designs targeted two frequency bands: 1.8 to 2.2 GHz (20% BW) and 1.8 to 2.7 GHz (40% BW). For the former, drain efficiency (DE) of 70% (+/–5%) and output power of 45.5 dBm (+/- 1.0dB) was measured while the latter achieved very promising efficiency of about 60% over the entire bandwidth.

Abstract Recently, the proliferating needs of high data rate communication systems are increasing the demand for higher frequency bands with broader bandwidth. The K-band (18~26.5 GHz), which include point to point communications (18~23 GHz), ISM band (24 GHz), and automotive radar applications (24 GHz and 22~29 GHz) is one of the most important frequency bands in modern wireless communication systems. This thesis mainly includes three parts. The first part of the thesis is the introduction to the principles and characteristics for active and passive components of CMOS process and the description of common transistors , such as BJT, CMOSFET, HBT and pHEMT. The principles of resistors, capacitors and inductors in simulations is shown. It is useful for the microwave circuit design to understand the structure and characteristics of active components and passive components in CMOS process. The second part describes the design principles and characteristics of power amplifier. The third part is the design and simulation of the 2 stages cascode configuration Class A power amplifier and the 3 stages cascode configuration Class A power amplifier with power combination. There are two important scaling trends that are making CMOS increasingly attractive for RF applications. One is the well known dramatic shrinkage of device size, so that transistors in the advanced process generation of CMOS have peak fT values in excess of 55 GHz.The other is the reverse scaling of interconnect. The thicker metal layer and more layers of wiring are enabling the realization of high-quality passive components which are critical for RF circuits. CMOS is the most attractive technology for its low cost, high yield and high level of integration. However, It is challenging to design a power amplifier with high output power. In the sub-micron CMOS technology, the challenges of CMOS power amplifier design include the low breakdown voltage, low transconductance (gm), and high substrate loss as compared with SiGe HBTs GaAs HBTs and InP-GaAs HBTs technologies. We made efforts in implementing a power amplifier at K-band. The design and simulation of two power amplifier is present. One is the 2 stages power amplifier, the other is the 3 stages power amplifier with power combination. In order to realize the inductive element and capacitive element in sub-milimeter wave or millimeter wave circuit design, the short stub microstrip line and open stub mircrostrip line are used in matching networks between all stages. The cascade configuration is effective structure to minimize Miller effect in high frequency. The peak gain of 2 stages power amplifier is 17 dB at 24 GHz and the saturation output power is 20 dBm. The OP1dB is over 16 dBm. The peak gain of 3 stages power amplifier with power combination is 20 dB at 24 GHz and the saturation output power is 20.5 dBm. The OP1dB is over 15 dBm.The power amplifier with the cascode configuration and power combination techniques is designed and simulated in TSMC 0.18 um CMOS process, which provides deep n-well, and MiM capacitors.

Class D power amplifier applies in high efficiency circuit. In hearing aid system, we require high power efficiency, low-voltage and low-power. The operation of frequency is low frequency. All the circuits are designed based on the TSMC 035 CMOS process technology. The supply voltage is 1.5V and the input signal is 4KHz. Simulation results show that the Class D power efficiency is high efficiency amplifier. When 0.3V of 2KHz input signal is applied, The maximum THD is 0.63% and static current is 4uA and the efficiency is 83.6%.

The primary advantage of Class D amplifier is high power efficiency (typically >90%). However, there are two problems in open-loop Class D design: Total Harmonic Distortion (THD) and output dc static current (the power efficiency will be degraded). The THD is rising from non-ideal sample carrier in Pulse Width Modulation circuit, and output dc static current is due to the non-match transfer characteristic in output stage. For designer to have such problems will be a large load. To improve these two problems, we proposed a Class D power amplifier with passive feedback design. Simulation and Measurement results show that the power efficiency is higher than 90% at 250Hz ~ 4KHz. Furthermore, the THD is less than 0.24% at 4 KHz in both simulation and experimental results.

This dissertation presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter with good potential for multi-mode operation. For enhancing the efficiency, a Class-E PA is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is proposed to be embedded in the HQPM for compensation. The use of such predistorted HQPM techniques can help reducing the average DC and RF input powers and the output feed-through levels so as to enhance power added efficiency and adjacent channel power rejection quite remarkably.

Using GaAs HBT provided by AWSC to construct Gummel Poon static model.then using the GaAs HBT processing of GCS to design MMIC power amplifier for the 1.9~2.0 GHz PCS system. This power amplifier exhibits an output power of 27dBm and a power added efficiency as high as 32% at an operation voltage of 3.4V.