This thesis consists of two parts. Part one presents a design of class-AB power amplifier in 0.15£gm pHEMT process, and establishes a nonlinear model with memory effects for the power amplifier using Volterra series. To observe the memory effects, two-tone continuous wave signals have been applied to the model to predict the phase variation between IM3H and IM3L as a function of tone spacing. In the meanwhile, a time-domain measurement technique for the third-order intermodulation responses using a digital storage oscilloscope has been developed to verify the modeled predictions on IM3H and IM3L. Comparison between modeled and measured results shows good agreement. Part two of this thesis is to study the CMOS power-combining techniques. At first, the pros and cons between series and parallel combining transformers are discussed. Then, a design of class-E power amplifier using a pair of parallel combining transformers for power combining is presented. Both simulated and measured results show that the presented Class-E power amplifier has a high power-added efficiency.

Abstract¡G This thesis studies the memory effect due to bias perturbation on digital predistortion technique, and employs multi-tone continuous wave signal and digital modulation signals with different bandwidth to discuss the performance of digital predistortion technique. Memory effect makes a great impact on the digital predistortion technique, and bias perturbation is one of the major causes. Lowering the bias perturbation can improve the effectiveness of digital predistortion technique. Another focus of this thesis is to design a Class E power amplifier in 0.18 £gm CMOS process. The power amplifier uses cascode structure to alleviate the breakdown voltage problem and employs power combining technique to achieve impedance transformation on chip for the purpose of increasing the output power and efficiency.

Le standard LTE permet l’accès au très haut débit mobile et évolue afind’adresser les applications embarquées de type objets connectés. Mais dans la perspectived’un émetteur-récepteur LTE fabriqué dans une technologie CMOS faible-coût ethautement intégrable, l’amplificateur de puissance (PA) reste le seul bloc actif non intégréà ce jour. De plus, l’utilisation de modulations en quadrature oblige la conceptiond’amplificateurs très linéaires, générant une consommation statique plus importante.Dans ce contexte, ces travaux de thèse portent sur la recherche de composants etde circuits permettant d’atteindre de fortes puissances de sortie et de résoudre le compromisentre la linéarité et la consommation du PA. Deux axes de travail sont identifiéset développés dans cette thèse. Le premier axe porte sur l’utilisation d’un transistor depuissance intégrable en technologie CMOS. Trois cellules de puissance basées sur ce composantsont présentées, de l’étude théorique aux résultats de mesure. Dans le second axede recherche, ce transistor est intégré dans une architecture avancée de PA entièrementréalisée en CMOS. Une méthode de conception de transformateurs intégrés est égalementdéveloppée. Le PA proposé est reconfigurable pour adresser les différents besoinsimposés par le standard LTE : puissance de sortie, haute linéarité et faible consommation. / The LTE standard has been intended for mobile communications. Focusingnot only on higher data rate, LTE now aims at an implementation for the Internetof Things (IoT). The main challenge, in the perspective of a LTE front-end fully manufacturedin a low-cost and high integration level CMOS technology, remains the design ofpower amplifiers (PA). Furthermore, the use of complex quadrature modulation resultsin stringent linearity requirements resulting in an important quiescent dc consumption.In this context, this work focuses on the research of devices and circuits generatinghigh output power and solving the compromise between linearity and consumption ofthe PA. Two strands of work are identified and developed in this thesis. The first oneuses a power transistor available in CMOS technology. Three power cells based on thisdevice are proposed, with detailed theoretical and experimental results. In the secondone, this transistor is then used in a fully-integrated CMOS PA. A design methodologyfor integrated transformers is also presented. The proposed fully-integrated PA is reconfigurablein order to address the main LTE challenges : output power, high linearity andlow consumption.

Ces travaux de thèse se concentrent sur la conception d'amplificateur de puissance MMIC large-bande haut rendement en technologie GaN pour des applications militaires de type radar et guerre électronique. Les objectifs principaux sont de proposer des structures innovantes de combinaison de puissance notamment pour réduire la taille des amplificateurs actuels tout en essayant d'améliorer leur rendement dans le même temps. Pour cela, une partie importante de ces travaux consiste au développement de combineurs de puissance ultra compactes et faibles pertes. Une fois ces combineurs réalisés et mesurés, ils sont intégrés dans des amplificateurs de puissance afin de prouver leur fonctionnalité et les avantages qu'ils apportent. Différents types d'amplificateur tant au niveau de l'architecture que desperformances sont réalisés au cours de ces travaux. / This work focus on the design of wideband and high efficiency GaN MMIC high power amplifiers for military applications such as radar and electronic warfare. The main objectives consist in finding innovative power combining structures in order to decrease the overall size of amplifiers and increasing their efficiency at the same time. For these matters, an important part of this work consisted in the design and realization of ultra compact and low loss power combiners. Once the combiners realized and measured, they are integrated into power amplifiers to prove their functionality and the advantages they bring. Several kind of amplifiers have been realized whether regrind their architecture or their performances.

The explosive growth of the wireless market has increased the demand for low-cost, highly-integrated CMOS wireless transceivers. However, the implementation of CMOS RF power amplifiers remains a formidable challenge. The objective of this research is to demonstrate the feasibility of CMOS RF power amplifiers by compensating for the RF performance disadvantages of CMOS technology. This dissertation proposes a parallel-combining transformer (PCT) as an impedance-matching and output-combining network. The results of a comprehensive analysis show that the PCT is a suitable solution for watt-level output power generation in cellular applications. To achieve high output power and high efficiency, the work presented here entailed the design of a class-E switching power amplifier in a 0.18-μm CMOS technology for GSM applications and, with the suggested power amplifier design technique, successfully demonstrated a fully-integrated RF front-end consisting of a power amplifier and an antenna switch. This dissertation also proposed an efficiency enhancement technique at power back-off. In an effort to save current in the power back-off while satisfying the EVM requirements, a class-AB linear power amplifier was implemented in a 0.18-μm CMOS technology for WLAN and WiMAX applications using a PCT as well as an operation class shift between class-A and class-B. Thus, the research in this dissertation provides low-cost CMOS RF power amplifier solutions for commercial products used in mobile wireless communications.

Phase control in microwave circuits is an impotant process. Especially, in certain applications such as phase array antennas, it is the main principle of opeation. In antenna arrays, each array element is fed by an individual oscillator. By controlling the phase of each oscillator, the radiation pattern and the RF power can be combined in space in certain directions. For such applications, phase shifters have been utilized extensively. However, their high costs, difficulties in design and efficiency are impotant disadvantages. More recently, another technique, &quot / Injection Locking&quot / or &quot / Phase Locking&quot / suggests to use a single reference signal injected into each oscilator element. Through this signal, the phase of the individual oscillators can be controlled and set to a desired value. Therefore, power combining in space or known as &quot / Spaial Power Combining&quot / is possible by using &quot / Phase Locking&quot / of individual oscillator elements. In this thesis, this new phase control technique is examined in theory and in application of a 1GHz oscillator system. A reference signal is injected into a voltage controlled oscillator, and the phase progression is obtained by tuning the oscilator&#039 / s free running frequency.

The development of millimeter-wave (30-300 GHz) sensors and communications systems has a long history of interest, spanning back almost six decades. In particular, mm-wave radars have applications as automotive radars, in remote atmospheric sensing applications, as landing radars for air and spacecraft, and for high precision imaging applications. Mm-wave radar systems have high angular accuracy and range resolution, and, while susceptible to atmospheric attenuation, are less susceptible to optically opaque conditions, such as smoke or dust. This dissertation document will present the initial steps towards a new approach to the creation of a mm-wave radar system at 94 GHz. Specifically, this dissertation presents the design, fabrication and testing of various components of a highly integrated mm-wave a 94 Ghz monopulse radar transmitter/receiver. Several architectural approaches are considered, including passive and active implementations of RF monopulse comparator networks. These architectures are enabled by a high-performance three-dimensional rectangular coaxial microwave transmission line technology known as PolyStrataTM as well as silicon-based IC technologies. A number of specific components are examined in detail, including: a 2x2 PolyStrata antenna array, a passive monopulse comparator network, a 94 GHz SiGe two-port active comparator MMIC, a 24 GHz RF-CMOS 4-port active monopulse comparator IC, and a series of V- and W-band corporate combining structures for use in transmitter power combining applications. The 94 GHz cavity-backed antennas based on a rectangular coaxial feeding network have been designed, fabricated, and tested. 13 dB gain for a 2 x 2 array, as well as antenna patterns are reported. In an effort to facilitate high-accuracy measurement of the antenna array, an E-probe transition to waveguide and PolyStrata diode detectors were also designed and fabricated. AW-band rectangular coaxial passive monopulse comparator with integrated antenna array and diode detectors have also been presented. Measured monopulse nulls of 31.4 dB in the ΔAZ plane have been demonstrated. 94-GHz SiGe active monopulse comparator IC and 24 GHz RF-CMOS active monopulse comparator RFIC designs are presented, including detailed simulations of monopulse nulls and performance over frequency. Simulations of the W-band SiGe active monopulse comparator IC indicate potential for wideband operation, with 30 dB monopulse nulls from 75-105 GHz. For the 24-GHz active monopulse comparator IC, simulated monopulse nulls of 71 dB and 68 dB were reported for the azimuthal and elevational sweeps. Measurements of these ICs were unsuccessful due to layout errors and incomplete accounting for parasitics. Simulated results from a series of rectangular coaxial power corporate power combining structures have been presented, and their relative merits discussed. These designs include 2-1 and 4-1 reactive, Wilkinson, and Gysel combiners at V- and W-band. Measured back-to-back results from Gysel combiners at 60 GHz included insertion loss of 0.13 dB per division for a 2-1 combination, and an insertion loss of 0.3 dB and 0.14 dB for "planar" and "direct" 4-1 combinations, respectively. At 94 GHz, a measured insertion loss of 0.1 dB per division has been presented for a 2-1 Gysel combination, using a back-to-back structure. Preliminary designs for a solid-state power amplifier (SSPA) structure have also been presented. Finally, two conceptual monopulse transceivers will be presented, as a vehicle for integrating the various components demonstrated in this dissertation. / Ph. D.

Les véhicules aériens sans pilote (UAV), souvent appelés drones, trouvent de nombreuses applications dans la vie. Les applications de drones nécessitent plusieurs indicateurs de performance essentiels tels que la couverture, la force du signal, la latence et la mobilité dans des scénarios. Par conséquent, l'utilisation des communications sans fil dans les drones est essentielle pour répondre à toutes les exigences. En raison des connexions au haut débit entre les drones et les utilisateurs pour transférer des données de haut volume à haute résolution, les dernières générations sans fil, comme la norme LTE, sont privilégiées. Il est évident que l'intégration de blocs de radiofréquence (RF) est essentielle pour construire un système sur puce et réduire la taille des drones. Dans ce contexte, cette thèse vise à développer un amplificateur de puissance (PA) innovant avec haute performance reconfigurable entièrement intégré qui adresse les différents besoins imposés par le standard LTE à utiliser dans les applications des UAV. Le PA entièrement intégré en CMOS 65 nm a pour objectif de fournir une puissance de sortie élevée et résoudre le compromis entre la linéarité et l’efficacité. Un transformateur à quatre enroulements est implémenté pour configurer le fonctionnement en multi modes du PA. La technique « segmented bias » permet au PA d’améliorer la linéarité. Le PA obtient non seulement des performances élevées en RF, mais démontre également un potentiel pour l'adopter dans la bande 5G inférieure. / Unmanned aerial vehicles (UAVs), often known as drones, have been finding numerous applications in life. Drones applications need several essential performance indicators such as coverage, signal strength, latency, and mobility under scenarios. Therefore, the use of wireless communications in drones is critical to address all requirements. Because of high-speed connections between drones and users to transfer high-resolution high-volume data, latest wireless generations, namely the LTE standard, are privileged. It is straightforward that the integration of RF blocks is essential to build a system-on-chip and shrink the size of drones. To answer the above question, this thesis aims to develop a fully integrated reconfigurable high-performance innovated PA that supports 4G LTE standard to be used in UAVs’ applications. The fully integrated 65-nm CMOS power amplifier (PA) provides a watt-level output power, addresses the linearity/efficiency trade-off. A four-winding transformer is implemented to configure the multi-mode operation of the PA. The “segmented bias” technique allows the PA to increase the linearity. The PA not only obtains high radiofrequency performances but also demonstrates a potential to adopt it design in the lower 5G band.

Dans le cadre des applications sans fil à 60GHz, l’amplificateur de puissance reste un des composants les plus compliqués à implémenter en technologie CMOS. Des modulations à enveloppe non constante obligent à concevoir des circuits hautement linéaires, conduisant à une consommation statique importante. La recherche de topologies et de techniques de linéarisation viables aux fréquences millimétriques fait l’objet de cette thèse. Dans un premier temps, un état de l’art des différents amplificateurs de puissance à 60GHz est dressé, afin d’en extraire l’ensemble des verrous technologiques limitant leurs performances. Suite à l’analyse des phénomènes physiques impactant les composants passifs, plusieurs structures d’amplificateurs élémentaires sont conçues dans les technologies 65nm et 28nm Bulk. Les topologies les plus pertinentes sont déduites de cette étude. Enfin, deux amplificateurs intégrant des techniques de combinaison de puissance et de linéarisation sont implémentés dans les technologies 65nm et 28nm FD-SOI. Ces deux circuits présentent les plus hauts facteurs de mérite ITRS publiés à ce jour. Le circuit en 28nm FD-SOI atteint en outre le meilleur compromis linéarité/consommation de l’état de l’art. / The CMOS 60GHz power amplifier (PA) remains one of the most design-challenging components. Indeed, a high linearity associated with a large back-off range are required due to complex modulated signals.In this context, this work focuses on the design of architectures and linearization techniques which are usable at millimeter-wave frequencies. First, a CMOS PA state of the art is presented to define all bottlenecks. Then, the physical phenomena impacting on passive device performances are described. Elementary PAs are implemented in CMOS 65nm and 28nm Bulk and the most suitable topologies are selected. Finally, two highly linear circuits are designed in 65nm Bulk and 28nm FD-SOI. They achieve the highest ITRS figures of merit reported to this day. In addition, the 28nm FD-SOI PA exhibits the best linearity/consumption tradeoff.

The demand for low power wireless transceiver implementations has been fueled by multiple applications in the recent decades, including cellular systems, wireless local area networks, personal area networks, biotelemetry and sensor networks. Dynamic range, which is set by linearity and sensitivity performance, is a critical design metric in many of these systems. Both linearity and sensitivity requirements continue to become progressively challenging in many systems due to greater spectrum usage and the need for high data rates respectively. The objective of this research is to investigate power-efficient circuit techniques for reducing the power requirement in receiver front-ends without compromising the dynamic range performance. In the first part of the dissertation, a low power receiver down-converter topology for enhancing dynamic range performance is presented. Current mode down-converters with passive mixer cores have been shown to provide excellent dynamic range performance. However, in contrast to a current commutating Gilbert cell, these down-converters require separate bias current paths for the RF transconductor and the baseband transimpedance amplifier. The proposed topology reduces the power requirement of conventional current mode passive down-converter by sharing the bias current between the transconductance and transimpedance stages. This is achieved without compromising the available voltage headroom for either stage, which is a limitation of bias-sharing based on the use of stacked stages. The dynamic range of the basic bias-current-shared topology is further enhanced through suppression of low frequency noise and IM3 products. Two variants of the down-converter, employing a broadband common-gate and a narrowband common-source input stage, are implemented in a 0.18-μm CMOS technology. The dynamic range performance of the architecture is analyzed. Finally, a prototype of a full direct-conversion receiver implementation with quadrature outputs and integrated LO synthesis is demonstrated. A power-efficient oscillator design for phase noise minimization is presented in the second part of this dissertation. This design is targeted towards multi-radio platforms where several communication links operate simultaneously over multiple frequency bands. Blockers from concurrently operating radios present a major design challenge. The blockers not only make the frontend linearity requirement more stringent but also degrade receiver sensitivity through reciprocal mixing with the phase noise sidebands of LO. Phase noise minimization is thus critical for ensuring high sensitivity in frequency bands where large blockers are present and not sufficiently attenuated by pre-select filters. A capacitive power combining technique in oscillators is introduced to improve phase noise performance. By combining this approach with current reuse, the phase noise is reduced at lower power, compared to conventional LC oscillators. This leads to improved power efficiency. Moreover, the technique mitigates modeling uncertainty arising from phase noise reduction through simultaneous impedance and current scaling. The mode selection in this oscillator, which employs multiple coupled resonators, is analyzed and the impact of coupling on far-out phase noise performance is discussed. Multi-mode oscillation can potentially arise in other oscillator topologies too, e.g., in multiphase oscillators. Mode selection in a widely used transistor-coupled quadrature oscillator is analyzed in detail in the final part of the dissertation. The analysis shows how cross-compression among multiple competing modes can lead to suppression of non-dominant modes in the steady state. / text