Le développement d'objets communicants dédiés aux applications Wireless Personal Area Network (WPAN) à 60GHz vise des débits de l'ordre du GBit/sec. Pour satisfaire la contrainte de faible coût, la technologie CMOS silicium est la plus adaptée. L'utilisation de cette technologie est un challenge en soi afin de concilier les aspects « pertes & rendement » vis à vis des contraintes de puissance. Le but de la thèse est de concevoir des amplificateurs de puissance opérant à 60GHz avec la technologie CMOS 65nm de STMicroelectronics. Cette démarche est progressive car il convient d'analyser puis d'optimiser les performances des composants passifs et actifs constituant l'amplificateur de puissance à l'aide des logiciels de simulations électromagnétique et microélectronique. Finalement, des amplificateurs de puissance ont été réalisés et leurs performances répondent au cahier des charges initialement défini. / Telecommunication industry claims for increasing data rate in wireless communication systems. The major demand of high data rate applications concerns a large panel of home multimedia exchanging data especially for the uncompressed HD data transfer. The 7GHz band around 60GHz is free of use and fulfils the short range gigabit communication requirements. CMOS technology is most appropriate since it drives a fast time to market with a low cost for high integration volume. However, the use of CMOS technology is challenging to satisfy loss and performance trade-off under power constraints. This thesis aims at designing power amplifiers operating at 60GHz with 65nm CMOS technology from STMicroelectronics. This approach is progressive because it is necessary to analyze and optimize the performance of passive and active components constituting the power amplifier using electromagnetic and microelectronics software. Finally, power amplifiers have been made. Their performances met specifications originally defined.

Chan Kwok-po. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Characterization of Nonlinearity in Power Amplifier --- p.6 / Chapter 2.1. --- Ideal Amplifier Representation --- p.6 / Chapter 2.2. --- Nonlinear Amplifier Representation --- p.7 / Chapter 2.2.1 --- Series Representation --- p.7 / Chapter 2.2.2 --- AM-AM and AM-PM Distortion --- p.7 / Chapter 2.2.3 --- Two-tone Intermodulation --- p.9 / Chapter 2.2.4 --- Nonlinearity on Digital Modulation Formats --- p.11 / Chapter Chapter 3 --- Linearization Techniques --- p.13 / Chapter 3.1. --- Power Back-off --- p.14 / Chapter 3.2. --- Feedback Technique --- p.15 / Chapter 3.3. --- Pre-distortion Technique --- p.16 / Chapter 3.4. --- Feed-forward Technique --- p.18 / Chapter 3.5. --- Linearization Systems with Signal Processing --- p.19 / Chapter 3.5.1 --- Envelope Elimination and Restoration (EER) --- p.19 / Chapter 3.5.2 --- Linear Amplification Using Nonlinear Components (LINC) --- p.20 / Chapter 3.5.3 --- Combined Analogue-locked Loop Universal Modulator (CALLUM) --- p.21 / Chapter 3.5.4 --- Linear Amplification Employing Sampling Techniques (LIST) --- p.21 / Chapter 3.6. --- Other Linearization Techniques --- p.22 / Chapter Chapter 4 --- Feed-forward Power Amplifier System --- p.23 / Chapter 4.1. --- General Description --- p.23 / Chapter 4.2. --- Adaptive Feed-forward Power Amplifier System --- p.25 / Chapter 4.2.1 --- Power Minimization --- p.28 / Chapter 4.2.2 --- Pilot Injection Technique --- p.29 / Chapter 4.2.3 --- Look-up-table Technique (Temperature Compensation) --- p.31 / Chapter 4.2.4 --- Correlation Based Feedback Control (Dual-loop) --- p.32 / Chapter 4.2.5 --- Correlation Based Feedback Control (Triple-loop) --- p.34 / Chapter 4.2.6 --- Digital Implementation on Adaptive FFPA --- p.35 / Chapter Chapter 5 --- DSP-based Adaptive FFPA Analysis --- p.37 / Chapter 5.1. --- System Architecture --- p.37 / Chapter 5.2. --- System Modeling --- p.39 / Chapter 5.3. --- Principle of Adaptation --- p.40 / Chapter 5.3.1 --- Adaptation in Error Extraction Loop --- p.40 / Chapter 5.3.2 --- Adaptation in Main-tone Suppression Loop --- p.43 / Chapter 5.3.3 --- Adaptation in Distortion Cancellation Loop --- p.44 / Chapter 5.3.4 --- Complex Adaptation --- p.46 / Chapter 5.4. --- Adaptation Performance Analysis --- p.47 / Chapter 5.4.1 --- Condition for Convergence --- p.47 / Chapter 5.4.2 --- Rate of Convergence --- p.48 / Chapter 5.4.3 --- Misadjustment --- p.49 / Chapter 5.4.4 --- Summary of the System Performance --- p.51 / Chapter 5.5. --- System Design Consideration --- p.51 / Chapter 5.5.1 --- Quadrature Sampling --- p.51 / Chapter 5.5.2 --- Data Processing --- p.52 / Chapter 5.6. --- Sensitivity Analysis --- p.55 / Chapter 5.6.1 --- Vector Representation --- p.55 / Chapter 5.6.2 --- Amplitude and Phase Matching --- p.56 / Chapter 5.6.3 --- Time-delay Matching --- p.58 / Chapter 5.7. --- Analog-to-digital Interface: Design Consideration --- p.60 / Chapter 5.7.1 --- Sampling Rate Consideration --- p.60 / Chapter 5.7.2 --- Finite Word-length --- p.61 / Chapter 5.8. --- Digital-to-analog Interface: Design Consideration --- p.63 / Chapter Chapter 6 --- New DSP Algorithms for High Performance Adaptive FFPA --- p.67 / Chapter 6.1. --- Variable Loop-gain Algorithm --- p.67 / Chapter 6.2. --- Variable Step-size Algorithm --- p.71 / Chapter 6.3. --- Least-mean-fourth Algorithm --- p.74 / Chapter Chapter 7 --- Implementation of DSP-based Adaptive FFPA --- p.79 / Chapter 7.1. --- Hardware Construction --- p.79 / Chapter 7.2. --- Experimental Results: LMS Algorithm --- p.82 / Chapter 7.3. --- Experimental Results: Variable Loop-gain Algorithm --- p.86 / Chapter 7.4. --- Experimental Results: Variable Step-size Algorithm --- p.88 / Chapter 7.5. --- Experimental Results: Lesat-mean-fourth Algorithm --- p.90 / Chapter Chapter 8 --- Conclusion --- p.92 / Appendix I Matlab Program for Computer Simulation of Adaptive FFPA --- p.A-l / Appendix II DSP Program for Experimental Adaptive FFPA --- p.A-5 / References --- p.R-1 / Author's Publications --- p.AP-1

Existing linearisation methods were examined to establish the requirements for a wideband power amplifier model. A range of memoryless models were investigated, in particular polynomial models. No suitable memoryless models were found. The shortcomings of the models were analysed and directions for future investigations presented. / thesis (MEng(ElectronicsEngineering))--University of South Australia, 2003.

<p>This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using LDMOS technologies. It involves a literature study of different SMPA concepts. Choosing the suitable class that achieves the high efficiency was the base stone of this</p><p>work. A push-pull class J power amplifier (PA) was designed with an integrated LC resonator inside the package using the bondwires and die capacitances. Analysis and motivation of the chosen class is included. Designing the suitable Input/Output printed circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC</p><p>bias network) was part of the work. This work is done by ADS simulation and showed a simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at 2.14 GHz. Study of the losses in each part of the design elements is also included.</p><p>Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB Gain.</p>

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 95-99).

Modern communication systems operate with high peak-to-average-power ratio (PAPR) over wide bandwidth. Linearity requirements force operation in a low efficient highly linear back-off region. Then increasing efficiency is becoming critical. One of the most promising technologies to accomplish this is using supply modulation, e.g. envelope tracking (ET) and envelope elimination and restoration (EER). Supply modulated systems have been studied extensively in the past years, but no systems have been presented with flexibility in the envelope amplifier circuit.   In this work the supply modulator amplifiers have been studied. The focus is on hybrid switching amplifier (HSA) as envelope amplifier. Two envelope amplifier prototypes P-I and P-II have been designed. They are both designed for 15W output but P-II has 28V maximum supply voltage and P-I has 15V maximum supply voltage. P-II developed in version A, using silicon (Si) based switching transistor and version B using gallium-nitride (GaN) switching transistor. The efficiency is limited to a maximum 97 % possible by the circuit components.   The linearity was mainly analyzed by AM-AM diagrams. P-I, P-IIA and P-IIB, were analyzed in simulations and measurements. Results show high possibility of improvement with digital processing, i.e. digital pre-distortion (DPD). Linearization will improve the overall performance in the supply modulator (SM) systems, improving the delay issues and distortion produced by the implementation of the system.   The developed flexible board has made it possible to investigate alternative technologies of ET, focused in the hybrid switching amplifier (HSA). This has given the possibility to compare the overall performance for a traditional Si based switch with the novel Ferdinand Braun Institute’s (FBH) GaN-HEMT based switch with regards to bandwidth, efficiency and non-linearities introduced by the envelope tracking amplifier. P-I and P-II show high efficiency (&gt; 60%) in results. For signals with adequate average power levels the efficiency is high, with around 70% efficiency for WCDMA signals. Phase distortions are evident already at a 5 MHz bandwidth.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by J. Stevenson Kenney. / Vita. Includes bibliographical references (leaves 157-165).

This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using LDMOS technologies. It involves a literature study of different SMPA concepts. Choosing the suitable class that achieves the high efficiency was the base stone of this work. A push-pull class J power amplifier (PA) was designed with an integrated LC resonator inside the package using the bondwires and die capacitances. Analysis and motivation of the chosen class is included. Designing the suitable Input/Output printed circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC bias network) was part of the work. This work is done by ADS simulation and showed a simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at 2.14 GHz. Study of the losses in each part of the design elements is also included. Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB Gain.

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