Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais. / This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The U.S. Army’s Hardened Subminiature Telemetry and Sensor Systems (HSTSS) program has engaged the M/A-COM Corporation to work in the development of a highly accurate, crystal controlled telemetry transmitter chip set to be used in Army and other U.S. military munitions. A critical factor in this work is the operating environment of up to 100,000-g launch accelerations. To support the Army in this project, M/A-COM is developing integrated Voltage Controlled Oscillators (VCO) for L and S band, a silicon synthesizer/phase locked loop (PLL) IC, and a family of power amplifiers. Lastly, the transmitter module will be miniaturized and hardened using M/A-COM’s latest chip-onboard mixed technology manufacturing capabilities. This new chip set will provide the telemetry engineer with unprecedented design flexibility. This paper will review the overall transmitter system design and provide an overview for each functional integrated circuit.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / Modern day digital modulation techniques in communication systems produce large peak-to-average ratios. To maintain linearity, power amplifiers have to operate at backed-off levels. This results in low efficiency with consequences such as high power consumption, short battery life and excessive heat in power amplifiers. A Doherty amplifier is an efficiency enhancement technique which increases an amplifier’s efficiency at backed-off levels. This thesis presents a design procedure for a Classical Doherty amplifier. A method where Sparameter measurements from a transistor are used to predict the transistor’s transmission phase response for varying input power is presented. This method is found to be accurate by comparing it to measurements done on a non-linear network analyser. The measured S-parameters are also used to design the Doherty amplifier at its predicted peak output power. Two Classical Doherty amplifiers are designed, manufactured and characterised. The measurements are performed on a custom measurement setup using in-house developed Matlab code to automate the measurements. The first Doherty amplifier used small-signal Siemens CFY30 GaAs FETs and the second Doherty amplifier used 10W Motorola MRF282 LDMOS transistors. The performance of both amplifiers is compared to similar balanced amplifiers and shows improvements in their efficiency. The improvement in efficiency for the 10W Doherty power amplifier in relation to a balanced amplifier is compared to results found in the literature and a good correspondence between the measured and published results were obtained.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010. / ENGLISH ABSTRACT: The thesis details the design, construction and experimental evaluation of 30W, 35W and 250W L-Band LDMOS Radar amplifiers. Each amplifier module contains an integrated high speed power supply in order to optimize RF pulse repeatability and to improve radar MTI factor (Moving Target Indication.) As part of the work, a pulsed RF measurement system for measuring the dynamic I-V curves of a power FET was developed. Work was also done on low impedance S-parameter measurement test fixtures for the characterisation of power FETs. These measurement systems generated design information which was used in the development of the L-Band power amplifiers / AFRIKAANSE OPSOMMING: Hierdie tesis beskryf die ontwerp, bou en experimentele evaluering van „n 30W, 35W en 250W L-band LDMOS radarversterker. Elke versterker bevat ook „n geintegreerde hoë-spoed kragbron om optimum RF pulsherhaalbaarheid te verseker en die radar se „MTI (Moving Target Indication)‟ te verbeter. „n RF-pulsmetingstelsel is ook ontwikkel om die dinamiese I-V kurwes van „n hoë-krag FET te meet. Verder is daar ook gewerk aan „n toetsopstelling vir lae-impedansie S-parameters om hoë-krag FETs te karakteriseer. Hierdie toetsopstelling is gebruik om ontwerpsdata te genereer wat gebruik is in die ontwerp van die L-band kragversterkers.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Cellular radio communication involves wireless transmission and reception of signals at radio frequencies (RF). Base stations house equipment critical to the transmission and reception of signals. Power amplifier (PA) is a crucial element in base station assembly. PAs are expensive, take up space and dissipate heat. Of all the elements in the base station, it is difficult to design and operate a power amplifier. New designs of power amplifiers are constantly tested. One of the most important components required to perform this test successfully is a circuit simulator model of an entire communication system that generates a standard test signal. Standard test signals 524,288 data points in length require 1080 hours to complete one test of a PA model. In order to reduce the time taken to complete one test, a 'simulated test signal,' was generated. The objective of this study is to develop an algorithm to generate this 'simulated' test signal such that its characteristics match that of the 'standard' test signal.

Lin Pui-Yu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 103-105). / Abstracts in English and Chinese. / Acknowledgement / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Nonlinear Phenomenon of Power Amplifier --- p.5 / Chapter 2.1. --- AM-AM and AM-PM Distortion --- p.5 / Chapter 2.2. --- Intermodulation Distortion --- p.7 / Chapter Chapter 3 --- Linearization Techniques --- p.10 / Chapter 3.1. --- Power Backoff --- p.11 / Chapter 3.2. --- Feedback --- p.12 / Chapter 3.3. --- Predistortion --- p.12 / Chapter 3.4. --- Feedforward --- p.14 / Chapter 3.5. --- Other Linearization Techniques --- p.15 / Chapter Chapter 4 --- Analysis of Feedforward Power Amplifier --- p.17 / Chapter 4.1. --- Feedforward Efficiency --- p.18 / Chapter 4.2. --- Design Criteria of the Auxiliary Amplifier --- p.20 / Chapter 4.3. --- Sensitivity Analysis --- p.21 / Chapter 4.3.1. --- Phase and Amplitude Mismatch --- p.22 / Chapter 4.3.2. --- Delay Mismatch --- p.23 / Chapter 4.3.3. --- Combined Effect --- p.25 / Chapter 4.3.4. --- Practical Consideration --- p.27 / Chapter 4.4. --- Other Design Criteria --- p.28 / Chapter Chapter 5 --- Adaptive Control Networks for FFPA --- p.29 / Chapter 5.1. --- Basic Principles of the Adaptive Control Network --- p.30 / Chapter 5.1.1. --- Lookup Table --- p.30 / Chapter 5.1.2. --- Power Minimization Vs. Correlation --- p.31 / Chapter 5.2. --- Analog Vs Digital Implementation of the Adaptive Control Network --- p.34 / Chapter 5.3. --- Techniques for Improving the Convergence Behaviour at the Distortion Cancellation Loop --- p.35 / Chapter 5.4. --- Important Notes on the Control Networks --- p.38 / Chapter Chapter 6 --- Novel Analysis of Adaptive FFPA --- p.40 / Chapter 6.1. --- Gradient algorithm --- p.40 / Chapter 6.2. --- Dual Loop Adaptive FFPA --- p.41 / Chapter 6.2.1. --- System Modeling --- p.42 / Chapter 6.2.2. --- Adaptation Behavior of the Distortion Extraction Loop --- p.44 / Chapter 6.2.3. --- Adaptation Behavior of the Distortion Cancellation Loop --- p.48 / Chapter 6.2.4. --- Accuracy Requirement of the Control Signals --- p.50 / Chapter 6.2.5. --- Effect of Delay Mismatch on the Convergence Accuracy --- p.51 / Chapter 6.2.6. --- Convergence Behaviors for Two Tone Input Signal --- p.52 / Chapter 6.2.6.1. --- Distortion Extraction Loop --- p.53 / Chapter 6.2.6.2. --- Distortion Cancellation Loop --- p.55 / Chapter 6.2.6.3. --- Simulation Results --- p.57 / Chapter 6.2.7. --- Convergence Behaviors for Digital Modulated Test signal --- p.60 / Chapter 6.2.7.1. --- Distortion Extraction Loop --- p.61 / Chapter 6.2.7.2. --- Distortion Cancellation Loop --- p.66 / Chapter 6.2.7.3. --- Simulation Results --- p.68 / Chapter 6.2.8. --- Comparison for the Adaptation Performance with Two Tone and Digital Modulated Test Signal --- p.70 / Chapter 6.3. --- Triple Loop Adaptive FFPA --- p.71 / Chapter 6.3.1. --- Adaptation Performance of the Additional Loop --- p.73 / Chapter 6.3.2. --- Adaptation Performance of the Distortion Cancellation Loop --- p.75 / Chapter 6.3.3. --- Improvement in Bias Error at the Distortion Cancellation Loop --- p.76 / Chapter 6.3.4. --- Effect of Delay Mismatch --- p.77 / Chapter 6.3.5. --- Simulation Results --- p.79 / Chapter Chapter 7 --- Implementation and Measured Performance of Triple Loop Adaptive FFPA --- p.85 / Chapter 7.1. --- Hardware Design --- p.85 / Chapter 7.1.1. --- Vector Modulator --- p.87 / Chapter 7.1.2 --- Complex Correlator --- p.88 / Chapter 7.2. --- Experimental Setup and Measured Results --- p.90 / Chapter Chapter 8 --- Conclusion --- p.95 / Appendix I Matlab Program for Simulation of Dual Loop Adaptive FFPA --- p.97 / Appendix II Matlab Program for Simulation of Triple Loop Adaptive FFPA --- p.100 / Reference --- p.103 / Author's Publication --- p.106

Leung Chi-Shuen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 82-89). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Review of Linearization Techniques --- p.4 / Chapter 2.1 --- Feedforward --- p.5 / Chapter 2.2 --- Feedback --- p.7 / Chapter 2.3 --- Predistortion --- p.10 / Chapter Chapter 3 --- The Volterra Series Method for Nonlinear Analysis --- p.12 / Chapter 3.1 --- Volterra Series Method --- p.13 / Chapter 3.2 --- Nonlinear Transfer Function --- p.14 / Chapter 3.3 --- Weakly Nonlinear Approximation --- p.18 / Chapter 3.4 --- Nonlinear Modeling --- p.19 / Chapter 3.5 --- Determination of Nonlinear Transfer Function --- p.22 / Chapter Chapter 4 --- Manifestation of Nonlinear Behavior --- p.25 / Chapter 4.1 --- Two-Tone Volterra Series Analysis --- p.25 / Chapter 4.2 --- Harmonic Distortion --- p.28 / Chapter 4.3 --- AM/AM and AM/PM --- p.29 / Chapter 4.4 --- Intermodulation Distortion --- p.31 / Chapter Chapter 5 --- The Generalized Baseband Signal Injection Method --- p.33 / Chapter 5.1 --- Generalized Baseband Signal Injection Method (GM) --- p.34 / Chapter 5.2 --- Application of GM to Predistorter-Amplifier Linearization --- p.38 / Chapter 5.2.1 --- Case 1: Standalone Amplifier without Injection --- p.40 / Chapter 5.2.2 --- Case 2: Injection to Amplifier Only --- p.41 / Chapter 5.2.3 --- Case 3: Injection to Diode Predistorter Only --- p.41 / Chapter 5.2.4 --- Case 4: Injection to Both Diode Predistorter and Amplifier --- p.42 / Chapter 5.3 --- Application of GM to Multi-Stage Amplifier Linearization --- p.43 / Chapter 5.3.1 --- Case 1: Amplifying System with No Signal Injection --- p.46 / Chapter 5.3.2 --- Case 2: Amplifying System with Single Injection Point --- p.47 / Chapter 5.3.3 --- Case 3: Amplifying System with Two Injection Points --- p.48 / Chapter Chapter 6 --- Experimental Setup and Measurements --- p.50 / Chapter 6.1 --- Experimental Setup --- p.51 / Chapter 6.1.1 --- Diode Predistorter --- p.51 / Chapter 6.1.2 --- Small Signal Amplifier --- p.54 / Chapter 6.1.3 --- Medium Power Amplifier --- p.58 / Chapter 6.1.4 --- Baseband Signal Generation Circuit --- p.61 / Chapter 6.1.5 --- Baseband Amplifiers --- p.63 / Chapter 6.2 --- Linearization of Amplifier with Predistortion Circuitry --- p.65 / Chapter 6.2.1 --- Two-Tone Test --- p.65 / Chapter 6.2.2 --- Vector Signal Test --- p.68 / Chapter 6.2.3 --- Dynamic Range Evaluation --- p.70 / Chapter 6.3 --- Linearization of Multi-Stage Amplifying System --- p.71 / Chapter 6.3.1 --- Determination of Transfer and Gain Coefficients --- p.71 / Chapter 6.3.2 --- Two-Tone Test --- p.74 / Chapter 6.3.3 --- Vector Signal Test --- p.77 / Chapter 6.3.4 --- Dynamic Range Evaluation --- p.79 / Chapter Chapter 7 --- Conclusion and Future Work --- p.80 / References --- p.82 / Author's Publications --- p.90

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise.

Ng, Yuen Sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Chapter 1. --- INTRODUCTION --- p.11 / Chapter 1.1 --- Motivation --- p.11 / Chapter 1.2 --- Specifications --- p.12 / Chapter 1.3 --- Organization of the Thesis --- p.16 / Chapter 1.4 --- References --- p.16 / Chapter 2. --- BASIC THEORY OF POWER AMPLIFIER AND TRANSMITTER FRONT-END --- p.18 / Chapter 2.1 --- Classification of Power Amplifier --- p.18 / Chapter 2.1.1 --- Class A --- p.20 / Chapter 2.1.2 --- Class B --- p.21 / Chapter 2.1.3 --- Class AB --- p.22 / Chapter 2.1.4 --- Class C --- p.23 / Chapter 2.1.5 --- Class D --- p.24 / Chapter 2.1.6 --- Class E --- p.25 / Chapter 2.1.7 --- Class F --- p.28 / Chapter 2.2 --- Figure-of-Mhrit of Power Amplifier --- p.28 / Chapter 2.2.1 --- Small Signal Analysis --- p.29 / Chapter 2.2.1.1 --- S-parameter --- p.29 / Chapter 2.2.1.2 --- Gain and Stability --- p.29 / Chapter 2.2.2 --- Large Signal Analysis --- p.32 / Chapter 2.2.2.1 --- 1-dB compression point --- p.33 / Chapter 2.2.2.2 --- Third-order intermodulation point --- p.33 / Chapter 2.2.2.3 --- Power Gain --- p.35 / Chapter 2.2.2.4 --- Drain Efficiency and Power Added Efficiency --- p.35 / Chapter 2.2.2.5 --- AM-AM and AM-PM conversion --- p.36 / Chapter 2.2.3 --- Modulation Analysis --- p.36 / Chapter 2.2.3.1 --- Constellation Diagram and Error Vector Magnitude --- p.36 / Chapter 2.3 --- Reference --- p.37 / Chapter 3. --- CIRCUIT DESIGN OF POWER AMPLIFIER --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Topology of the Power Amplifier Design --- p.39 / Chapter 3.3 --- Design in Power Amplifier --- p.40 / Chapter 3.2.1 --- Power Stage --- p.40 / Chapter 3.2.2 --- Driver Stage and Input matching --- p.46 / Chapter 3.4 --- Simulation Result on Power Amplifier --- p.49 / Chapter 3.5 --- Layout consideration --- p.50 / Chapter 3.6 --- Measurement Result on Power Amplifier --- p.51 / Chapter 3.4.1 --- Small signal measurement --- p.52 / Chapter 3.4.2 --- Large signal measurement --- p.55 / Chapter 3.4.3 --- Modulation measurement --- p.56 / Chapter 3.7 --- Performance Summary --- p.58 / Chapter 3.8 --- Reference --- p.59 / Chapter 4. --- CIRCUIT DESIGN OF TRANSMITTER FRONT-END --- p.60 / Chapter 4.1 --- Introduction --- p.60 / Chapter 4.2 --- Topology of the Transmitter Front-End Design --- p.61 / Chapter 4.3 --- Design in transmitter front-end circuit --- p.64 / Chapter 4.2.1 --- I/Q Modulator --- p.64 / Chapter 4.2.2 --- Power Amplifier --- p.66 / Chapter 4.2.3 --- On-chip LC Balun --- p.72 / Chapter 4.4 --- Simulation Result of the Transmitter Front-End Design --- p.74 / Chapter 4.5 --- Layout consideration --- p.75 / Chapter 4.6 --- Measurement Result of the Transmitter Front-End Design --- p.76 / Chapter 4.4.1. --- Transmitter Front-End Measurement --- p.77 / Chapter 4.4.1.1 --- Output Reflection coefficient --- p.77 / Chapter 4.4.1.2 --- Large Signal Measurement --- p.78 / Chapter 4.4.1.3 --- Modulation Measurement --- p.81 / Chapter 4.4.2. --- LC Balun Measurement --- p.84 / Chapter 4.7 --- Performance Summary of the transmitter front-end circuit --- p.86 / Chapter 4.8 --- Reference --- p.89 / Chapter 5. --- CONCLUSION --- p.90 / Chapter 6. --- FUTURE WORK --- p.91