CAPES / Este trabalho apresenta uma estratégia de controle PI adaptativo baseada em curvas de perfil gaussiano, onde os ganhos são função do erro de referência. A estratégia foi aplicada em sistemas de condicionamento de energia. Primeiramente em sistemas de detecção de ângulo de fase (PLL) para sistemas monofásicos, onde foram testados dois sistemas, o pPLL e o DSOGI-pPLL. Foi aplicada posteriormente no controlador de tensão e corrente de um filtro ativo de potência paralelo monofásico. O controlador adaptativo conseguiu melhorar o desempenho do sistema e também reduzir o taxa de distorção harmônica da corrente compensada. / This work presents a strategy of adaptive PI control based on Gaussian profile curves, where the gains are functions of reference error. The strategy was applied in energy conditioning systems. Firstly in a phase-locked loop (PLL) for single phase systems, where two techniques were tested, the pPLL and DSOGI-pPLL. After it was applied in a voltage and current control of single-phase parallel active power filter. The adaptive control was able to improve the system performance and also decrease the total harmonic distortion of compensated current.

Este trabalho apresenta o projeto e implementação de um sistema UPS (Uninterruptible Power Supply) Line-Interactive monofásico com compensação ativa de potência série e paralela, o qual realiza a supressão de harmônicos e compensação de afundamentos e elevações da tensão da rede elétrica, além de manter a tensão na carga regulada. Adicionalmente, a UPS atua na compensação de potência reativa e supressão dos harmônicos de corrente da carga, resultando em uma efetiva correção do fator de potência. Desse modo, com a rede elétrica presente, a UPS opera como filtro ativo universal realizando a compensação da corrente de entrada, bem como da tensão de saída. Quando a rede elétrica está ausente, a UPS alimenta a carga com tensão regulada e com baixa taxa de distorção harmônica. Para este fim, dois conversores monofásicos PWM são empregados, sendo estes chamados de filtro ativo série (FAS), o qual atua como fonte de corrente senoidal e o filtro ativo paralelo (FAP), o qual atua como fonte de tensão senoidal, ambos controlados para operar em fase com a tensão da rede. Com o objetivo de extrair a corrente de referência senoidal de compensação, usada no controle do FAS, é utilizado um algoritmo baseado no sistema de eixo de referência síncrona (SRF-Synchronous Reference Frame). Para a obtenção da referência da tensão senoidal de saída, assim como as coordenadas do vetor unitário síncrono utilizados pelo algoritmo SRF, um sistema de detecção de ângulo de fase (PLL-Phase Locked Loop) monofásico é utilizado. Ensaios experimentais, bem como simulações computacionais são realizados a fim de confirmar o desenvolvimento teórico e avaliar o desempenho dinâmico e estático do sistema UPS. / This work presents a single-phase Line-interactive UPS System implementation with series and parallel active power-line compensation, which performs harmonic suppression and voltage sag/swell compensation of the utility voltage, as well as maintaining the output voltage regulated. Additionally, the UPS performs reactive power compensation and harmonic suppression of the load current, resulting in an effective power-factor correction. Thereby, when the incoming power grid is present, the UPS works as a universal active power filter compensating the input current and output voltage. On the other hand, when an outage occurs, the UPS feeds the load with regulated and harmonic free voltage. For this purpose, two single-phase PWM converters are employed, which are referred as series active power filter (SAPF), which acts as a sinusoidal current source, and parallel active power filter (PAPF), which acts as a sinusoidal voltage source. Both the APFs are controlled to be in phase with the input voltage. In order to extract the sinusoidal compensation reference current, used in SAPF control, an algorithm based on synchronous reference frame (SRF) is used. The sinusoidal output voltage reference and the coordinates of the synchronous vector are obtained by using a phase-locked loop (PLL) algorithm. Experimental results and computational simulations are presented to confirm the theoretical development and evaluate both the dynamic and steady state behavior of the UPS system.

Este trabalho apresenta o projeto e implementação de um sistema UPS (Uninterruptible Power Supply) Line-Interactive monofásico com compensação ativa de potência série e paralela, o qual realiza a supressão de harmônicos e compensação de afundamentos e elevações da tensão da rede elétrica, além de manter a tensão na carga regulada. Adicionalmente, a UPS atua na compensação de potência reativa e supressão dos harmônicos de corrente da carga, resultando em uma efetiva correção do fator de potência. Desse modo, com a rede elétrica presente, a UPS opera como filtro ativo universal realizando a compensação da corrente de entrada, bem como da tensão de saída. Quando a rede elétrica está ausente, a UPS alimenta a carga com tensão regulada e com baixa taxa de distorção harmônica. Para este fim, dois conversores monofásicos PWM são empregados, sendo estes chamados de filtro ativo série (FAS), o qual atua como fonte de corrente senoidal e o filtro ativo paralelo (FAP), o qual atua como fonte de tensão senoidal, ambos controlados para operar em fase com a tensão da rede. Com o objetivo de extrair a corrente de referência senoidal de compensação, usada no controle do FAS, é utilizado um algoritmo baseado no sistema de eixo de referência síncrona (SRF-Synchronous Reference Frame). Para a obtenção da referência da tensão senoidal de saída, assim como as coordenadas do vetor unitário síncrono utilizados pelo algoritmo SRF, um sistema de detecção de ângulo de fase (PLL-Phase Locked Loop) monofásico é utilizado. Ensaios experimentais, bem como simulações computacionais são realizados a fim de confirmar o desenvolvimento teórico e avaliar o desempenho dinâmico e estático do sistema UPS. / This work presents a single-phase Line-interactive UPS System implementation with series and parallel active power-line compensation, which performs harmonic suppression and voltage sag/swell compensation of the utility voltage, as well as maintaining the output voltage regulated. Additionally, the UPS performs reactive power compensation and harmonic suppression of the load current, resulting in an effective power-factor correction. Thereby, when the incoming power grid is present, the UPS works as a universal active power filter compensating the input current and output voltage. On the other hand, when an outage occurs, the UPS feeds the load with regulated and harmonic free voltage. For this purpose, two single-phase PWM converters are employed, which are referred as series active power filter (SAPF), which acts as a sinusoidal current source, and parallel active power filter (PAPF), which acts as a sinusoidal voltage source. Both the APFs are controlled to be in phase with the input voltage. In order to extract the sinusoidal compensation reference current, used in SAPF control, an algorithm based on synchronous reference frame (SRF) is used. The sinusoidal output voltage reference and the coordinates of the synchronous vector are obtained by using a phase-locked loop (PLL) algorithm. Experimental results and computational simulations are presented to confirm the theoretical development and evaluate both the dynamic and steady state behavior of the UPS system.

Abstract The modern wireless communication techniques are aiming on increasing bandwidth and the number of carriers for higher data rate. This sets challenging linearity requirements for RF power amplifiers (PAs). Unfortunately, high linearity can only be obtained at the cost of efficiency. In order to improve the performance of the PA, in-depth understanding of nonlinear behaviour is mandatory. This calls for techniques that can give componentwise information of the causes of the distortion. The aim of this thesis is to develop a technique that can provide such information. This thesis proposes a detailed distortion analysis technique that is based on frequency domain fitting of polynomial models. Simulated large-signal spectra are used for fitting as these contain the necessary information about the large-signal bias point and amplitude range. Moreover, in the frequency domain the delays are easy to compensate, and detailed analysis to any fitted tone can be performed. The fitting procedure as such is simple but becomes difficult in multi-dimensional nonlinearities if the controlling voltages correlate strongly. In this thesis the solvability and reliability of the fitting procedure is increased by numerical operations, model-degree reduction and by using different excitations. A simplified Volterra method is used to calculate the distortion contributions by using the fitted model. The overall distortion is analysed by calculating the voltage response of the contributions of each nonlinearity to the terminal nodes of the device by the use of linear transfer functions of the circuit. The componentwise analysis is performed by phasor presentation enabling the cancelling mechanisms to be seen. The proposed technique is implemented on top of harmonic balance simulation in an APLAC circuit simulator in which extensive distortion simulations are performed. The technique relies on the existing device model and thus the fitted model can be only as accurate as the particular simulation model. However, two different RF PAs are analysed that show a good agreement between measurements and simulations. The proposed technique is verified with several test cases including amplitude dependent amplitude and phase distortion, intermodulation distortion sweet spots, bandwidth dependent memory effects and impedance optimization. The main finding of the detailed analysis is that the distortion is a result of several cancelling mechanisms. In general, cubic nonlinearity of transconductance is dominating the in-band distortion but is cancelled by the 2nd-degree nonlinearity that is mixed to the fundamental band from envelope and 2nd harmonic bands that is usually the main cause of memory effects.

Abstract The main emphasis in modern RF power amplifier (PA) research is on improving linearity while at the same time maintaining reasonably good efficiency, for which purpose external linearization in the form of feedforward or predistortion is often used. Linearity and linearization can be considered from both a fundamental signal (amplitude and phase conversions, AM-AM & AM-PM) and an intermodulation distortion (IMD) regeneration point of view, and since a study of intermodulation gives more information on the behaviour of an amplifier, linearity is studied in this thesis by analysing the amplitude and phase of IM components under varying signal conditions, i.e. as functions of temperature, modulation bandwidth and amplitude. To study the behaviour of IM components analytically, a Volterra model including electro-thermal distortion mechanisms is developed and a simulation technique is introduced to determine how easily the amplifier can be linearized. An S-parameter characterization method for extracting the Volterra model and the simulation model is developed, and the amplitude and phase dependences of the IM components are shown by means of measurements performed by a novel technique developed here. The results show that the behaviour of IM components is more complicated than had commonly been expected. Three techniques are developed for eliminating the frequency dependence of IM components, impedance optimization, envelope filtering and envelope injection. In the envelope injection technique, a low frequency envelope signal is added to the input of the amplifier in order to improve both the bandwidth and amplitude range of the memoryless predistortion. The functionality of envelope injection is demonstrated by Volterra calculations, simulations and measurements, and the technique is applied to 1W, 1.8 GHz common-emitter BJT and common-source MESFET amplifiers. IM cancellation better than 20 dB is achieved over a wide range of bandwidths and amplitudes. It is concluded that an inherently linear amplifier is not necessarily easy to linearize any further using external techniques, but that the part of the distortion that varies with bandwidth and amplitude can be cancelled out using envelope injection and the remaining memoryless distortion by means of a simple polynomial RF predistorter. This results in good cancellation of distortion, and since both envelope injection and RF predistortion consume little power, both good efficiency and linearity can be achieved.

In modern wireless communication systems, a base station typically serves a few hundred users within its cell coverage. To combat the near-far problem – the situation where a nearby user’s strong cellular signal masks the cellular signal of a faraway user – base stations continually enforce power control. That is, nearby users must lower their transmit power. In CDMA technology, power control can be as large as 70-80dB. At low power outputs, this greatly impacts the performance of the RF power amplifier (PA) in the cellular device. For small RF drives, the magnitude of the output RF current approaches the magnitude of the DC current and thus the efficiency suffers. Operating the RF PA in class C operation improves the efficiency, but results in poor linearity. Several methods of so-called dynamic biasing have been proposed. These strategies entail lowering the bias of the PA as the RF drive increases. The proposed methods, however, fail to explain how to achieve linearity and low third-order intermodulation distortion. Additionally, the methods utilize open-loop implementations. This work presents a novel dynamic biasing topology that results in a much improved linear class C PA. The topology utilizes a closed loop that cleverly senses the operating conditions of the "power device." Particularly, the loop operates on the principle of keeping the conduction angle remarkably constant and thereby ensuring linearity. The work details a thorough design methodology that should provide assistance to a designer wanting to implement the topology in an RF integrated circuit. Agilent ADS simulations and laboratory results from a functional PCB prototype bring merit to the topology.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

No description available.

This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-toSource voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18µm CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.