Kwok Pui-ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves [79]-85). / Abstracts in English and Chinese. / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter CHAPTER 2 --- NONLINEAR BEHAVIOR OF RF POWER AMPLIFIERS --- p.5 / Chapter 2.1 --- Single Tone Excitation --- p.6 / Chapter 2.1.1 --- AM-AM Conversion --- p.7 / Chapter 2.1.2 --- AM-PM Conversion --- p.9 / Chapter 2.2 --- Two-Tone Excitation --- p.11 / Chapter 2.2.1 --- Intermodulation Distortion --- p.12 / Chapter 2.3 --- Digitally Modulated Signal Excitation --- p.13 / Chapter 2.3.1 --- Spectral Regeneration --- p.14 / Chapter 2.3.2 --- Adjacent Channel Power Ratio (ACPR) --- p.16 / Chapter CHAPTER 3 --- LINEARIZATION TECHNIQUES --- p.18 / Chapter 3.1 --- pre-distortion --- p.20 / Chapter 3.2 --- Feed-forward Techniques --- p.23 / Chapter 3.3 --- Harmonics Control Techniques --- p.24 / Chapter CHAPTER 4 --- SPECTRAL REGROWTH ANALYSIS USING VOLTERRA SERIES METHOD --- p.26 / Chapter 4.1 --- Introduction To Volterra Series Analysis --- p.27 / Chapter 4.1.1 --- Linear and Nonlinear Systems --- p.27 / Chapter 4.1.2 --- Evaluation of Volterra transfer function --- p.29 / Chapter 4.1.3 --- Volterra Series Analysis of Spectral Regrowth --- p.31 / Chapter 4.2 --- Nonlinear Model of GaAs MESFET Device --- p.33 / Chapter 4.3 --- Evaluation Of Nonlinear Responses --- p.35 / Chapter 4.3.1 --- First-Order Response --- p.36 / Chapter 4.3.2 --- Second-Order Response --- p.38 / Chapter 4.3.3 --- Third-Order Response --- p.39 / Chapter CHAPTER 5 --- EFFECT OF HARMONIC TUNING ON SPECTRAL REGROWTH --- p.42 / Chapter 5.1 --- Simulation of Digitally Modulated Signal --- p.43 / Chapter 5.2 --- Effect of Source Second Harmonic Termination --- p.44 / Chapter CHAPTER 6 --- EXPERIMENTAL VERIFICATION --- p.48 / Chapter 6.1 --- Circuit Design and Construction --- p.49 / Chapter 6.2 --- Setup and Measurement --- p.55 / Chapter 6.3 --- Experimental Results --- p.56 / Chapter 6.3.1 --- Small Signal Measurement --- p.56 / Chapter 6.3.2 --- Single Tone Characterization --- p.57 / Chapter 6.3.3 --- Two-Tone Characterization --- p.59 / Chapter 6.3.4 --- ACPR Characterization --- p.60 / Chapter 6.4 --- Comparison of Measurement and Simulation --- p.66 / Chapter CHAPTER 7 --- NONLINEAR TRANSCONDUCTANCE COEFFICIENTS EXTRACTION --- p.68 / Chapter 7.1 --- Large Signal Model --- p.69 / Chapter 7.2 --- Extraction of Nonlinear Transconductance --- p.71 / Chapter 7.2.1 --- Extraction of g1 --- p.71 / Chapter 7.2.2 --- Extraction of g2 and g3 --- p.72 / Chapter CHAPTER 8 --- CONCLUSION --- p.76 / FUTURE WORK RECOMMENDATION --- p.78 / REFERENCE

Depuis plusieurs décennies, les générateurs forts courants sont utilisés dans différents domaines comme l’étude des matériaux, la radiographie ou la fusion par confinement inertiel. Ces générateurs sont capables de délivrer des impulsions de courant de plusieurs millions d’ampères avec des fronts de montée inférieurs à la microseconde. Plusieurs projets à travers le monde ont, aujourd’hui, pour but d’améliorer encore et encore le gradient de courant des impulsions transmises à la charge. De nombreux schémas d’amplificateurs de puissance, dont le rôle est de jouer à la fois sur l’amplitude du courant de charge et sur son temps de montée, ont ainsi été testés. Le multiplicateur de courant dynamique (DLCM pour Dynamic Load Current Multiplier) fait partie de ces concepts novateurs permettant de contourner les limitations des générateurs de puissances pulsées actuels. Il est composé d’un réseau d’électrodes (servant d’autotransformateur), d’un extrudeur de flux dynamique (basé sur l’implosion d’un réseau de fils cylindrique) et d’un commutateur à fermeture sous vide. Dans la thèse, le principe de fonctionnement du DLCM est analysé d’un point de vue théorique par le biais de simulations de type circuits électriques et magnétohydrodynamiques. Une étude spécifique portant sur l’organe principal du DLCM est réalisée. Il s‘agit du commutateur à fermeture sous vide. Ainsi, après une phase de dimensionnement à l’aide d’outils de simulations électrostatiques, deux versions de commutateurs sont validées expérimentalement dans des conditions proches de celles d’un tir très fort courant. Enfin, des tirs sur le générateur SPHINX du CEA Gramat, capable de délivrer une impulsion de courant de 6MA en 800ns (sur charge Z-pinch), sont exposés pour retracer l’évolution du dispositif. Les résultats probants obtenus permettent, au final, de valider le concept DLCM connecté à une charge de type compression isentropique. / For several decades, high power generators are used in various fields such as materials research, radiography or inertial confinement fusion. These generators are capable of delivering current pulses of several millions of amperes with rise times below 1 microsecond. Several projects around the world are, today, trying to improve again and again the current gradient of pulses delivered to the load. Many concepts of power amplifiers, whose role is to optimize both the amplitude of the load current and its rise time, were tested. The Dynamic Load Current Multiplier (DLCM) is one of those innovating concepts used to overcome the existing pulsed power generators limitations. It is made up of concentric electrodes (for autotransformer), a dynamic flux extruder (based on the implosion of cylindrical wire array) and a vacuum closing switch. In this these, the operating principle of the DLCM is theoretically analyzed through electrical and magneto hydrodynamic simulations. A specific study of the DLCM key component is performed. This is the vacuum closing switch. Thus, after a design phase using electrostatic simulation tools, two versions of switches are experimentally validated in conditions similar to those of a very high current shot. Finally, shots on the SPHINX facility located at the CEA Gramat, capable of delivering a current pulse of 6MA in 800ns (on Z-pinch load), are exposed to trace the evolution of this device. The convincing results are used, ultimately, to validate the DLCM concept connected to an isentropic compression experiment load.

The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.

Dans le cadre des applications sans fil à 60GHz, l’amplificateur de puissance reste un des composants les plus compliqués à implémenter en technologie CMOS. Des modulations à enveloppe non constante obligent à concevoir des circuits hautement linéaires, conduisant à une consommation statique importante. La recherche de topologies et de techniques de linéarisation viables aux fréquences millimétriques fait l’objet de cette thèse. Dans un premier temps, un état de l’art des différents amplificateurs de puissance à 60GHz est dressé, afin d’en extraire l’ensemble des verrous technologiques limitant leurs performances. Suite à l’analyse des phénomènes physiques impactant les composants passifs, plusieurs structures d’amplificateurs élémentaires sont conçues dans les technologies 65nm et 28nm Bulk. Les topologies les plus pertinentes sont déduites de cette étude. Enfin, deux amplificateurs intégrant des techniques de combinaison de puissance et de linéarisation sont implémentés dans les technologies 65nm et 28nm FD-SOI. Ces deux circuits présentent les plus hauts facteurs de mérite ITRS publiés à ce jour. Le circuit en 28nm FD-SOI atteint en outre le meilleur compromis linéarité/consommation de l’état de l’art. / The CMOS 60GHz power amplifier (PA) remains one of the most design-challenging components. Indeed, a high linearity associated with a large back-off range are required due to complex modulated signals.In this context, this work focuses on the design of architectures and linearization techniques which are usable at millimeter-wave frequencies. First, a CMOS PA state of the art is presented to define all bottlenecks. Then, the physical phenomena impacting on passive device performances are described. Elementary PAs are implemented in CMOS 65nm and 28nm Bulk and the most suitable topologies are selected. Finally, two highly linear circuits are designed in 65nm Bulk and 28nm FD-SOI. They achieve the highest ITRS figures of merit reported to this day. In addition, the 28nm FD-SOI PA exhibits the best linearity/consumption tradeoff.

<p>Abstract</p><p>In this thesis, a measurement system was set to perform comprehensive measurements on RF power amplifiers. Data obtained from the measurements is then processed mathematically to obtain three dimensional graphs of the basic parameters affected or generated by nonlinearities of the amplifier i.e. gain, efficiency and distortion. Using a class AB amplifier as the DUT, two sets of signals – both swept in power level and frequency - were generated to validate the method, a two-tone signal and a WCDMA signal. The three dimensional plot gives a thorough representation of the behavior of the amplifier in any arbitrary range of spectrum and input level. Sweet spots are consequently easy to detect and analyze. The measurement setup can also yield other three dimensional plots of variations of gain, efficiency or distortion versus frequencies and input levels. Moreover, the measurement tool can be used to plot traditional two dimensional plots such as, input versus gain, frequency versus efficiency etc, making the setup a practical tool for RF amplifiers designers.</p><p>The test signals were generated by computer then sent to a vector signal generator that generates the actual signals fed to the amplifier. The output of the amplifier is fed to a vector signal analyzer then collected by computer to be handled. MATLAB® was used throughout the entire process.</p><p>The distortion considered in the case of the two-tone signals is the third order intermodulation distortion (IM3) whereas Adjacent Channel Power Ratio (ACPR) was considered in the case of WCDMA.</p>

Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.

This dissertation presents a novel large signal modeling approach which can be used to accurately model CMOS transistors used in millimeter-wave CMOS power amplifiers. The large signal model presented in this work is classified as an empirical compact device model which incorporates temperature-dependency and device periphery scaling. These added features allow for efficient design of multi-stage CMOS power amplifiers by virtue of the process-scalability. Prior to the presentation of the details of the model development, background is given regarding the 90nm CMOS process, device test structures, de-embedding methods and device measurements, all of which are necessary preliminary steps for any device modeling methodology. Following discussion of model development, the design of multi-stage 60GHz Class AB CMOS power amplifiers using the developed model is shown, providing further model validation. The body of research concludes with an investigation into designing a CMOS power amplifier operating at frequencies close to the millimeter-wave range with a potentially higher-efficiency class of power amplifier operation. Specifically, a 24GHz 130nm CMOS Inverse Class F power amplifier is simulated using a modified version of the device model, fabricated and compared with simulations. This further demonstrates the robustness of this device modeling method.

The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless communication market. Although CMOS technology can provide most building blocks in RF transceivers, the implementation of CMOS RF power amplifiers is still a challenging task. The objective of this research is to develop design techniques to implement fully-integrated multi-mode power amplifiers using CMOS technology. In this dissertation, a load modulation technique with tunable matching networks and a pre-distortion technique in a multi-stage PA are proposed to support multi-communication standards with a single PA. A fully-integrated dual-mode GSM/EDGE PA was designed and implemented in a 0.18 um CMOS technology to achieve high output power for the GSM application and high linearity for the EDGE application. With the suggested power amplifier design techniques, fully-integrated PAs have been successfully demonstrated in GSM and EDGE applications. In Addition to the proposed techniques, a body-switched cascode PA core is also proposed to utilize a single PA in multi-mode applications without hurting the performance. With the proposed techniques, a fully-integrated multi-mode PA has been implemented in a 0.18 um CMOS technology, and the power amplifier has been demonstrated successfully for GSM/EDGE/WCDMA applications. In conclusion, the research in this dissertation provides CMOS RF power amplifier solutions for multiple standards in mobile wireless communications with low cost and high integration.

This thesis describes a unique approach of turning on and off transistor cores to reconfigure low-noise amplifiers. A small footprint single-pole, single-throw switch is optimized for low insertion loss and high isolation. A narrowband (non-switchable) LNA is developed as a basis of comparison for reconfigurable designs. The optimized switch is incorporated into different switchable transistor core architectures. These architectures are investigated to determine their ability to reconfigure amplifier performance. One switchable transistor core topology is integrated into a cascode LNA design. An in depth stability analysis employing the S-probe technique is used to help improve the reliability of the cascode design. In addition, a single-pole, double-throw transmit/receive switch, as well as a deserializer are developed to help support the LNA block in a reconfigurable phased-array radar system. This type of flexible radar design is very beneficial in challenging electromagnetic environments.

With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.