In recent years, there has been an extensive effort to develop low-cost implementations of radio frequency integrated circuits for consumer applications. This thesis is a research effort in the design and implementation of integrated RF CMOS Power Amplifiers (PAs). A significant challenge in the implementation of RF CMOS ICs is the impact of device, package and passive element parasitics on circuit performance. Passive components are a critical part of any RF IC design, and a process optimized for digital circuits results in inductors and capacitors with very high parasitics. In this work, we have developed a compact model for inductors fabricated in a digital CMOS process. Measured results have been used to further refine the accuracy of the inductor model. This model has been used to predict the impact of inductor parasitics on the performance of RFICs, and is also simple enough to be included in a CAD tool for circuit optimization. We have also studied the operation of Class A, B and C power amplifiers and highlighted design issues which are specific to the implementation of integrated PAs. It is shown that inductor loss has the most critical impact on the performance of integrated PAs. A custom CAD tool, based on the simulated annealing algorithm, has been developed to optimize the performance of power amplifiers for maximum efficiency in the presence of package, device and passive element parasitics. This CAD tool simulates the process of load-pull to determine the optimum large-signal load impedance for the PA, and optimizes the matching network design based on the trade-off between the loss in the matching network and its impedance transformation properties. This trade-off is relevant in the case of high-loss matching networks only, as is the case in integrated RF CMOS ICs. This CAD tool has been used to optimize the efficiency of balanced 100mW CMOS PAs operating at 900MHz. Measured results validate the design and optimization process outlined in this work. It is demonstrated that in the design of RF CMOS ICs, significant benefits can be gained by incorporating parasitics into the design process by means of CAD optimization. The CAD tool developed is an effort towards achieving this goal. It is further proposed that CAD optimization is an essential part of the design of RF CMOS ICs in general, and with the development of improved package, device and passive element models, CAD optimization will replace the "tuning" of RF circuits and result in robust, fully-integrated implementations of RF circuits. / Graduation date: 1999

SiC MESFETs and GaN HEMTs have an enormous potential in high-power amplifiers at microwave frequencies due to their wide bandgap features of high electric breakdown field strength, high electron saturation velocity and high operating temperature. The high power density combined with the comparably high impedance attainable by these devices also offers new possibilities for wideband power microwave systems. In this thesis, Class C switching response of SiC MESFET in TCAD and two different generations of broadband power amplifiers have been designed, fabricated and characterized. Input and output matching networks and shunt feedback topology based on microstrip and lumped components have been designed, to increase the bandwidth and to improve the stability. The first amplifier is a single stage 26-watt using a SiC MESFET covering the frequency from 200-500 MHz is designed and fabricated. Typical results at 50 V drain bias for the whole band are, 22 dB power gain, 43 dBm output power, minimum power added efficiency at P 1dB is 47 % at 200 MHz and maximum 60 % at 500 MHz and the IMD3 level at 10 dB back-off from P 1dB is below ‑45 dBc. The results at 60 V drain bias at 500 MHz are, 24.9 dB power gain, 44.15 dBm output power (26 W) and 66 % PAE. In the second phase, two power amplifiers at 0.7-1.8 GHz without feed back for SiC MESFET and with feedback for GaN HEMT are designed and fabricated (both these transistors were of 10 W). The measured maximum output power for the SiC amplifier at Vd = 48 V was 41.3 dBm (~13.7 W), with a PAE of 32 % and a power gain above 10 dB. At a drain bias of Vd= 66 V at 700 MHz the Pmax was 42.2 dBm (~16.6 W) with a PAE of 34.4 %. The measured results for GaN amplifier are; maximum output power at Vd = 48 V is 40 dBm (~10 W), with a PAE of 34 % and a power gain above 10 dB. The SiC amplifier gives better results than for GaN amplifier for the same 10 W transistor. A comparison between the physical simulations and measured device characteristics has also been carried out. A novel and efficient way to extend the physical simulations to large signal high frequency domain was developed in our group, is further extended to study the class-C switching response of the devices. By the extended technique the switching losses, power density and PAE in the dynamics of the SiC MESFET transistor at four different frequencies of 500 MHz, 1, 2 and 3 GHz during large signal operation and the source of switching losses in the device structure was investigated. The results obtained at 500 MHz are, PAE of 78.3%, a power density of 2.5 W/mm with a switching loss of 0.69 W/mm. Typical results at 3 GHz are, PAE of 53.4 %, a power density of 1.7 W/mm with a switching loss of 1.52 W/mm. / Report code: LIU-TEK-LIC-2008:32

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width. In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor. Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.

The continuous increase in wireless usage forces an immense pressure on wireless communication in terms of increased demand and spectrum scarcity. Service providers for communication services had no choice but to allocate new parts of the spectrum and present new communication standards that are more spectrally efficient. Communication is not only limited to mobile phones but recently attention has been given to intelligent transportation systems (ITS) where cars will be given a significant place in the communication network. Vehicular Ad-Hoc Network (VANET) is already assigned a slice of the spectrum at 5.9GHz using the IEEE802.11p standard also known as Dedicated Short-Range Communication (DSRC); however, this assignment will have limited range and functionality at first, and users are expected to depend on existing wireless mobile channels for some services such as video streaming and car entertainment. Therefore, it is essential to integrate existing wireless mobile communication standards into the skeleton of ITS at launch and most probably permanently. An investigation was carried out regarding the existing communication standards including wireless local area networks (WLAN) and it was found that frequency bands from 400MHz up to 6GHz are being used in various regions around the world. It is also noted that current state of the art transceivers are composed of several transmitter front-ends targeting certain bands and standards. However, the more standards to be supported the more components to be added and the higher the cost not to mention the limited space in mobile devices. Multimode Multiband (MMMB) transmitters are therefore proposed as a potential solution to the existing redundancy in the number of front-end paths in modern transmitters. Broadband amplifiers are an essential part of any MMMB transmitter and they are also among the most challenging especially for high power requirements. This work explains why single ended topologies with efficiencies higher than 50% have a fundamental bandwidth limit such that the highest frequency of operation must be lower than twice the lowest frequency of operation. Hence, Push-Pull amplifier topology is being proposed as it was found that it has inherent broadband capabilities exceeding those of other topologies with comparable efficiency. The major advantage of Push-Pull power amplifiers is its capability of isolating the even harmonics present in the even mode operation of a Push-Pull amplifier from the less critical odd mode harmonics and the fundamental frequency. This separation between even and odd signals comes from the inclusion of a Balun at the output of push-pull amplifiers. Such separation makes it possible to operate amplifiers beyond the existing limit of single ended power amplifiers. To prove the concept, several Baluns were designed and tested and a comparison was made between different topologies in terms of balance, bandwidth and odd and even mode performances; moreover, to illustrate the concept a Push-Pull power amplifier design was implemented using the multilayer Low Temperature Co-fired Ceramics (LTCC) technology with a bandwidth ratio of more than 100%.

Power Amplifiers (PAs) are the key building blocks of the emerging wireless radios systems. They dominate the power consumption and sources of distortion, especially when driven with modulated signals. Several approaches have been devised to characterize the nonlinearity of a PA. Among these approaches, dynamic amplitude (AM/AM) and phase (AM/PM) distortion characteristics are widely used to characterize the PA nonlinearity and its effects on the output signal in power, frequency or time domains, when driven with realistic modulated signals. The inherent nonlinear behaviour of PAs generally yield output signals with an unacceptable quality, an undesirable level of out-of-band emission, high Error Vector Magnitudes (EVMs) and low Adjacent Channel Power Ratios (ACPRs), which usually fail to meet the established performance standards. Traditionally, PAs are forced to operate deeply in their back-off region, far from their power capacity, in order to pass the mandatory spectrum mask (ACPR requirement) and to achieve acceptable EVM. Despite its simplicity, this solution is increasingly discarded, as it leads to cost and power inefficient radios. Alternatively, several linearization techniques, such as feedback, feed-forward and predistortion, have been devised to tackle PA nonlinearity and, consequently, improve the achievable the linearity versus power efficiency trade-off. Among these linearization techniques, the Digital Pre-Distortion (DPD) technique consists of incorporating an extra nonlinear function before the PA, in order to preprocess the input signal to the PA, so that the overall cascaded systems behave linearly. The overall linearity of the cascaded system (DPD plus PA) relies primarily on the ability of the DPD function to produce nonlinearities that are equal in magnitude and out-of-phase to those generated by the PA. Hence, a good understanding and accurate modeling of PA distortions is a crucial step in the construction of an adequate DPD function. This thesis explores DPD through techniques based on Artificial Neural Networks (ANNs). The choice of ANN as a modeling tool was motivated by its proven strength in modeling dynamic nonlinear systems. This thesis starts by providing a summary of the PA nonlinearity problem background, as well as an overview of the most well-known linearization techniques, with a special focus on DPD techniques. The thesis then discusses ANN structures and the learning parameters. Finally, a novel Two Hidden Layers ANN (2HLANN) model is suggested to predict the dynamic nonlinear behaviour of wideband PAs. An extensive validation of the 2HLANN model demonstrates its excellent modeling accuracy and linearization capability.

No description available.

This dissertation presents a study of linearization techniques that have been applied to power amplifiers in the cellular communication industry. The objective of this work is to understand the limitations of power amplifiers, specifically the limitations introduced by the use of spectrally efficient modulation schemes. The digitization of communication systems has favored the use of new techniques and technologies capable of increasing the efficiency of costly power amplifiers. The work explores traditional and digital linearization systems; an algorithm based on the principles of natural recombination is proposed to directly address the limitations of previous embodiments. Previous techniques, although effective, have significant implementation costs that increase exponentially with the increasing signal bandwidths. The proposed software-hardware architecture significantly reduces implementation costs and the overall complexity of the design without sacrificing performance. To fulfill the requirements of this study, multiple systems are implemented through simulation and closed-loop hardware. Both simulation and hardware embodiments meet the expected performance metrics, providing validation of the proposed algorithm. The application of the algorithm to memory power amplifier linearization is a new approach to adaptive digital pre-distortion using narrowband feedback. The work will show performance improvements on an amplifier with memory effects suggesting that this technique can be employed as a lower-cost solution to meet requirements when compared to typical system implementations.

This study is focus on the integration and miniaturess of the active circuit and antennas. Recently, the monolithic microwave integrated circuits have been mature in communication markets and the associated handsets are interesting in the quality and profile. The antenna plays a role as a radiator in wireless system. Therefore, the performance dominates the quality of communication. The aspect of the antenna usually occupies the majority communication hardware¡¦s area. Comparing many front end circuit elements, the challenges in the antennas will be more crucial. Therefore, it has well merits in designing high integration and bandwidth antennas. Based on the integration of the active circuits stage and antennas, this work presents the aperture coupled active antenna with harmonic suppression and broadband dual feeds circularly polarized patch antenna. Utilizing the bented aperture and insertion of narrow rectangular slots on excitation edge for shifting the high order harmonic components from the active stage, the harmonic suppression characterization is implemented by the above approach. The other active antenna, braodband dual feeds circularly polarized antenna, is achieved with spatial power combining. The subject aims the different excitated patch structures and replacing the periodic feeding lines as active circuits in the discussion. Relative to the conventional 50 Ohm feeds, the mechanics of the feeds are modified with stepped impedance resonators and stubs at the same physical wave length condition for achieving the integration of the antenna and the circuit. Besides, this antenna can exhibit excellent behavior and compact the size in the effective frequency range.

Future wireless communication systems will have higher data transmission rates and energy efficiencies than those used today. This fact raises serious challenges to the design of conventional transceiver architectures. This doctoral research develops energy-efficient RF transmitters and receivers for next-generation wireless communications. It begins with a theoretical analysis of the injection locking of oscillators and a modified Class-E power amplifier (PA) for use in developing the proposed transmitter and receiver. Based on the presented theory, a novel envelope elimination and restoration (EER)/polar transmitter using injection-locked oscillators (ILOs) and a novel cognitive polar receiver using two ILO stages are proposed. The EER/polar transmitter combines the approaches of EER/polar modulation and injection locking to achieve linear amplification with a high gain and high efficiency. Experimental results demonstrate its effectiveness for delivering WCDMA and EDGE signals. Additionally, the cognitive polar receiver utilizes two ILO stages to extract the modulation envelope and phase components of a received nonconstant envelope modulation signal without using a phase-locked loop (PLL)-based carrier recovery circuit. Experiments are conducted to verify the feasibility of the novel architecture by performing £k/4 DQPSK and QPSK demodulation. Rigorous theoretical analysis and experimental verification prove that both the proposed transmitter and the receiver are effective for energy-efficient wireless communications.