Doctor of Philosophy / Department of Physics / Kristan L. Corwin / The focus of this research is improving the pulse output energy of a mid-IR pulsed acetylene-filled Hollow-core Optical Fiber Gas LASer (HOFGLAS) system. Pump pulses and acetylene molecules interact with each other inside hollow-core photonic crystal fiber that effectively confines light and allows for strong gain. This results in lasing at 3.11 μm and 3.17 μm lines based on population inversion of acetylene molecules, which are optically pumped at rotational-vibrational overtones near 1.5 μm using 1 ns pulse duration from an optical parametric amplifier (OPA). This acetylene laser operates with no cavity mirrors because of a high gain in a single pass configuration. There are few laser sources in the mid-IR region while there are many applications for having a laser source in this range such as remote sensing, hazardous chemical detection, and breath analysis. This adds to the importance of the acetylene-filled HOFGLAS system. Some of the applications like remote sensing require high power. So, we moved toward power scaling this laser system by optimizing the laser operation through maximizing the OPA alignment to improve its modal content using longer length of fiber to increase the interaction length and improving the beam quality of the mid-IR emissions. The highest pulse energy ever obtained in the 3 µm mid-IR region from the acetylene-filled HOFGLAS after applying the improvements is reported here (1.4 μJ). Higher mid-IR pulse energies can be achieved by improving the pulse energy achievable from the OPA pump source and working with longer pulse duration to decrease the bandwidth of the OPA. This operation demonstrates many novel properties of acetylene-filled pulsed mid-IR hollow-core fiber lasers. The excellent spatial beam quality at highest power and phenomenological scaling of saturation power and efficiency with pressure that we observe point to the promise of power scaling and motivate further development of numerical models of the laser for deeper insight into these effects. M² measurement method was used to examine spatial beam quality and it was found to be fiber-dependent. For the improved setup, M² was investigated at several input pump powers in addition to the reproducibility checks. M² of 1.14 at the maximum output power motivates for beam combining to scale to higher power. The independence of efficiency on pressure is an evidence for reaching higher mid-IR power at a pressure where saturation behavior does not exist. achieving the highest mid-IR power to date, 1.4 μJ, encourages for building higher power OPA to produce high power mid-IR emissions. Taken as a whole, this laser exhibits novel behavior that motivates both numerical/theoretical investigation and further efforts to scale to higher powers.

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LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.