High-performance computing (HPC) systems have become power limited. For instance, the U.S. Department of Energy set a power envelope of 20MW in 2008 for the first exascale supercomputer now expected to arrive in 2021--22. Toward this end, we seek to improve the greenness of HPC systems by improving their performance per watt at the allocated power budget. In this dissertation, we develop a series of models and techniques to manage power at micro-, meso-, and macro-levels of the system hierarchy, specifically addressing data movement and heterogeneity. We target the chip interconnect at the micro-level, heterogeneous nodes at the meso-level, and a supercomputing cluster at the macro-level. Overall, our goal is to improve the greenness of HPC systems by intelligently managing power. The first part of this dissertation focuses on measurement and modeling problems for power. First, we study how to infer chip-interconnect power by observing the system-wide power consumption. Our proposal is to design a novel micro-benchmarking methodology based on data-movement distance by which we can properly isolate the chip interconnect and measure its power. Next, we study how to develop software power meters to monitor a GPU's power consumption at runtime. Our proposal is to adapt performance counter-based models for their use at runtime via a combination of heuristics, statistical techniques, and application-specific knowledge. In the second part of this dissertation, we focus on managing power. First, we propose to reduce the chip-interconnect power by proactively managing its dynamic voltage and frequency (DVFS) state. Toward this end, we develop a novel phase predictor that uses approximate pattern matching to forecast future requirements and in turn, proactively manage power. Second, we study the problem of applying a power cap to a heterogeneous node. Our proposal proactively manages the GPU power using phase prediction and a DVFS power model but reactively manages the CPU. The resulting hybrid approach can take advantage of the differences in the capabilities of the two devices. Third, we study how in-situ techniques can be applied to improve the greenness of HPC clusters. Overall, in our dissertation, we demonstrate that it is possible to infer power consumption of real hardware components without directly measuring them, using the chip interconnect and GPU as examples. We also demonstrate that it is possible to build models of sufficient accuracy and apply them for intelligently managing power at many levels of the system hierarchy. / Doctor of Philosophy / Past research in green high-performance computing (HPC) mostly focused on managing the power consumed by general-purpose processors, known as central processing units (CPUs) and to a lesser extent, memory. In this dissertation, we study two increasingly important components: interconnects (predominantly focused on those inside a chip, but not limited to them) and graphics processing units (GPUs). Our contributions in this dissertation include a set of innovative measurement techniques to estimate the power consumed by the target components, statistical and analytical approaches to develop power models and their optimizations, and algorithms to manage power statically and at runtime. Experimental results show that it is possible to build models of sufficient accuracy and apply them for intelligently managing power on multiple levels of the system hierarchy: chip interconnect at the micro-level, heterogeneous nodes at the meso-level, and a supercomputing cluster at the macro-level.

Master of Science / Department of Electrical and Computer Engineering / Noel Schulz / Many situations can cause a fault on a shipboard power system, especially in naval battleships. Batteries and ultra-capacitors are simulated to be backup energy storage devices (ESDs) to power the shipboard power system when an outage or damage occurs. Because ESDs have advantages such as guaranteed load leveling, good transient operation, and energy recovery during braking operation, they are commonly used for electrical ship applications. To fulfill these requirements, an energy management subsystem (EMS) with a specific control algorithm must connect ESDs to the dc link of the motor drive system. In this research, the real-time simulation of shipboard power system (SPS), bidirectional DC-DC converter, EMS, and ESDs are designed, implemented, and controlled on OPAL-RT system to test SPS survivability and ESD performance in various speed operations.

In order to run and manage resource-intensive high-performance applications, large-scale computing and storage platforms have been evolving rapidly in various domains in both academia and industry. The energy expenditure consumed to operate and maintain these cloud computing infrastructures is a major factor to influence the overall profit and efficiency for most cloud service providers. Moreover, considering the mitigation of environmental damage from excessive carbon dioxide emission, the amount of power consumed by enterprise-scale data centers should be constrained for protection of the environment.Generally speaking, there exists a trade-off between power consumption and application performance in large-scale computing systems and how to balance these two factors has become an important topic for researchers and engineers in cloud and HPC communities. Therefore, minimizing the power usage while satisfying the Service Level Agreements have become one of the most desirable objectives in cloud computing research and implementation. Since the fundamental feature of the cloud computing platform is hosting workloads with a variety of characteristics in a consolidated and on-demand manner, it is demanding to explore the inherent relationship between power usage and machine configurations. Subsequently, with an understanding of these inherent relationships, researchers are able to develop effective power management policies to optimize productivity by balancing power usage and system performance. In this dissertation, we develop an autonomic power-aware system management framework for large-scale computer systems. We propose a series of techniques including coarse-grain power profiling, VM power modelling, power-aware resource auto-configuration and full-system power usage simulator. These techniques help us to understand the characteristics of power consumption of various system components. Based on these techniques, we are able to test various job scheduling strategies and develop resource management approaches to enhance the systems' power efficiency.

L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numériques, en particulier pour les applications tirant leur énergie de batteries ou de l'environnement. La miniaturisation technologique n'est plus suffisante pour atteindre les niveaux de consommation requis. Ce travail de recherche propose ainsi de nouvelles conceptions de circuits pour la génération d'horloge flexible, la mesure de puissance et de température ainsi que l'intégration de ces blocs au sein de systèmes sur puce complets.Le multiplieur de fréquence innovant en boucle ouverte proposé permet l'adaptation rapide de la fréquence générée (53MHz 0.5V - 889MHz 0.9 V). Sa surface réduite (981µm2) et faible consommation (0.45pJ/cycle à 0.5 V) facilitent son intégration dans des systèmes à basse consommation. Le capteur de puissance instrumente un convertisseur de tension switched-capacitor; validé sur deux architectures différentes, il permet une mesure de la puissance d'entrée et de sortie avec une précision de 2.5% à 6%. Enfin, un nouveau principe de capteur de température est proposé. Il exploite une méthode de calibration par body-biasing sur caisson n et un système numérique intégré pour la compensation de non-linéarité. Enfin, cette thèse illustre la manière dont ces circuits peuvent être intégrés pour assurer la gestion de consommation de systèmes complexes. Un travail de modélisation du body-biasing est proposé, illustrant sa complémentarité avec la gestion de tension d'alimentation. Puis trois exemples de stratégies de gestion de la consommation sont proposées au sein de systèmes complets. / Energy efficiency has become a key metric for digital SoC, especially for applications relying on batteries or energy harvesting. Hence, this work proposes new designs for on-chip flexible clock generator, power monitor and temperature sensor as well as the integration of those blocks within complete SoC.The novel open-loop clock multiplier architecture enables fast frequency scaling and is implemented to operate on the same voltage-frequency range as a digital core ((53MHz 0.5V - 889MHz 0.9 V). The achieved extremely low area (981µm2) and power consumption 0.45pJ/cycle 0.5 V) also ease its integration within low power SoC. The proposed power monitor instruments switched capacitor DC-DC converters, which are standard components of low voltage SoCs. The monitor has been demonstrated over two different converters topologies and provides a measurement of both the converter input and output power within 2.5% to 6% accuracy. Last, a new principle of temperature sensor is proposed. It leverages single n well body-biasing for calibration and integrated digital logic for large non-linearity correction. It is expected to achieve within 1C accuracy 0.1nJ / sample and 225 µm2 probe area. Then, this work illustrates how those circuits can be integrated within complex SoCs power management strategies. First, a modeling study of body biasing highlights the benefits it can provide in complement to voltage scaling, accounting for a wide temperature range. Last, three example of power management are proposed at SoC level.

O trabalho visa desenvolver uma metodologia para avaliar o impacto do emprego das tecnologias de percepção de uso no ambiente residencial quanto às reduções da demanda por energia elétrica e emissões de CO2. Tais tecnologias são: eliminador de stand-by, gerenciador de energia em computadores e sensor de presença. Inicialmente são selecionadas cargas residenciais e coletados seus dados para compor um banco de dados que será utilizado nas análises. Cada carga e conjunto destas recebe a tecnologia adequada, sendo então calculado o consumo evitado e o investimento relacionado. Foram criados perfis de funcionamento das cargas (6, 8 e 10h) para reproduzir diferentes comportamentos dos usuários e cenários de utilização das cargas (A, B e C) para a análise de sensibilidade. Foram feitos estudos de caso com diferentes modelos residenciais, sendo calculados: consumo e demanda de energia evitados e redução de emissões (considerando um conjunto de residências similares). Também foi realizada a análise de viabilidade econômica da implantação, considerando o Custo Marginal de Expansão do setor elétrico (visão do investidor em infraestrutura) e as tarifas de energia elétrica (visão do consumidor). Os resultados apontam para uma contribuição relevante, em termos de eficiência energética, do emprego de tais tecnologias, representando 35 a 85 MW evitados e redução de emissões de 59 a 145 mil tCO2/ano, dependendo do tipo de modelo residencial adotado, considerando a cidade de São Paulo. A análise de viabilidade econômica por payback simples apontou os seguintes retornos de investimento: 7,2 a 15,5 anos e 2,3 a 7,4 anos para o investidor em infraestrutura e consumidor, respectivamente, dependendo do modelo residencial. Já a análise por Custo da Energia Economizada (CEE) apontou a viabilidade para o consumidor em todos os modelos residenciais, exceto o de tarifa social. Desta forma, o emprego de tais tecnologias pode contribuir de forma importante com a postergação da expansão da matriz energética, resultando em redução de investimentos em expansão e das emissões de CO2 relacionados à geração de energia elétrica, além de poder representar economia na conta de energia dos moradores. / This study aims to develop a methodology to evaluate the utilization impact of the use perception technologies in residential environment in reducing the demand for electricity and CO2 emissions. These technologies are: standby killer, power manager for computers and presence sensor. Initially, residential loads are selected and their data is collected to compose a database that will be used in the analyzes. Each load and load group receives the appropriate technology and then are calculated the avoided consumption and the acquisition investment of the technology. Loads operational profiles (6, 8 and 10h) were created to represent user behaviors and loads usage scenarios (A, B and C) were created to conduct a sensitivity analysis. Case studies were carried out with different residential models, where were calculated: avoided electricity consumption and electric energy demand and CO2 emission reduction (considering a set of similar residences). Also, it was conducted the analysis of economic implantation viability, considering the Expansion Marginal Cost of the electric sector (infrastructure investor view) and the electric energy rates (customer view). The results point out to a relevant contribution, in terms of energy efficiency, of the utilization of such technologies, representing 35 to 85 MW of avoided demand and emission reductions of 59 to 145 thousand tCO2, per year, depending on the residential model type adopted, considering Sao Paulo city region. The analysis of economic implantation viability by payback point out the following investments returns: from 7.2 to 15.5 years and from 2.3 to 7.4 years to infrastructure investor and customer, respectively, depending on the residence model. The analysis by Cost of Saved Energy point out the implementation viability for the costumer in all residential models, except the social tariff. Thus, the use of such technologies can significantly contribute to the postponement of the energetic matrix expansion, resulting in reduction of expansion investments and of CO2 related to electric energy generation, besides can represent savings in the residents energy bill.

Near-field wireless power transfer (WPT) technology facilitates the energy autonomy of heterogeneous systems, significantly augmenting complementary metal-oxide-semiconductor field-effect-transistor (CMOS) technology. In low-power wearable devices, existing power conditioning integrated circuits do not maximize the power factor (PF) for rectification and power conversion efficiency (PCE) due to multiple conversion. Additionally, there is no core power management for the entire power flow. The majority of the research focuses on active rectifiers, which reduce the turn-on voltage for rectification. Certain studies target the output voltage regulation via feedback to the transmitter or direct battery charging without power maximization. Firstly, this study investigates a high-power factor WPT front-end circuit that is namely the mono-periodic switching rectifier (MPSR) and implemented in a 0.18µm 1.8V/5V CMOS process. Integrated phase synchronizers are used to align the waveshape of a wirelessly-coupled sinusoidal voltage source in a receiving coil to the corresponding conducting current. Using this approach, the PF can be increased from roughly 0.6 to unity without requiring any wireless or wired feedback to the transmitter. The proposed MPSR can also provide AC-DC rectification, and step up and down the sinusoidal voltage source's peak amplitude using a pulse-width modulator. Measured voltage conversion ratios range between 0.73X and 2X, and the PF can be boosted up to unity. Secondly, the wireless power system-on-chip (WPower-SoC) is proposed and implemented in a 0.18µm 1.8V/3.3V CMOS process. The WPower-SoC integrating power management can provide rectification, output voltage regulation, and battery charging. Additionally, the implementation of feedforward envelope detection (FED) can reduce the variation in a wireless power link and improve load transient responses. Simulated results demonstrate that 5% of the output voltage regulation is improved when an output load changes. Moreover, the FED reduces approximately 40% of the transient response time. Overshoot and undershoot voltages are decreased by 23% and 26.5%, respectively. The measured output voltage regulates at 3.42V and can supply output power up to 342mW. A temperature sensor as part of the power management core remains active when the WPT receivers enter sleep mode to prolong the battery usage time. In the final part of this study, a nano-watt high-accuracy temperature sensing core is implemented in a 0.18µm 1.8V/3.3V CMOS process that can self-compensate the temperature shift without the need for additional compensating techniques that consume extra power.

Les capteurs sans fil ont un avenir prometteur c’est pourquoi leur développement est àl’origine de nombreuses recherches. Leur autonomie reste cependant un problème à résoudre.Les travaux de cette thèse se concentrent précisément sur cette problématique : trouverune stratégie permettant aux capteurs d’être autonomes en énergie.L’énergie nécessaire à l’alimentation du capteur, quel que soit son mode de fonctionnement,doit en effet être récupérée de l’environnement dans lequel le capteur se trouve. Deplus, en cas d’absence ou d’insuffisance d’énergie environnante, le fonctionnement du capteurdoit pouvoir perdurer. À cela s’ajoute la nécessité de connaitre à tout instant la quantitéd’énergie disponible afin de pouvoir maintenir un niveau de charge constant et ainsi prolongerla vie du capteur. Enfin, toute cette gestion de l’énergie doit pouvoir garantir le meilleurrendement possible.Cette étude a conduit à la conception et au test d’un circuit en technologie CMOS 90nm.Ce même circuit a été intégré dans les capteurs sans fil d’un réseau en cours de développement.Et enfin, une méthode permettant de connaitre le niveau d’énergie embarquée a étémise au point et pourra permettre à l’avenir la conception d’un nouveau circuit de power managementpour capteurs autonomes en énergie. / Wireless sensors have a bright future so their development is causing a lot of research.However, their autonomy is still an issue.This work focuses on this problem : find a strategy for the sensors to be autonomous.The energy required to power the sensor, whatever its working mode, must indeed be harvestedfrom the environment wherein the sensor is located. Moreover, in case of absence ora lack of available energy, the sensor has to keep working. Additionnaly the state-of-chargehas to be known in real time in order to extend the sensor lifetime. Finally, the energy managementhas to give the highest efficiency.This study led to the design and the test of a circuit in CMOS 90nm technology. Thiscircuit was integrated in wireless sensors for networks under development. Finally, a methodto estimate the level of energy in the sensor has been developed and will allow to design anew circuit of power management for wireless sensor network.

O trabalho visa desenvolver uma metodologia para avaliar o impacto do emprego das tecnologias de percepção de uso no ambiente residencial quanto às reduções da demanda por energia elétrica e emissões de CO2. Tais tecnologias são: eliminador de stand-by, gerenciador de energia em computadores e sensor de presença. Inicialmente são selecionadas cargas residenciais e coletados seus dados para compor um banco de dados que será utilizado nas análises. Cada carga e conjunto destas recebe a tecnologia adequada, sendo então calculado o consumo evitado e o investimento relacionado. Foram criados perfis de funcionamento das cargas (6, 8 e 10h) para reproduzir diferentes comportamentos dos usuários e cenários de utilização das cargas (A, B e C) para a análise de sensibilidade. Foram feitos estudos de caso com diferentes modelos residenciais, sendo calculados: consumo e demanda de energia evitados e redução de emissões (considerando um conjunto de residências similares). Também foi realizada a análise de viabilidade econômica da implantação, considerando o Custo Marginal de Expansão do setor elétrico (visão do investidor em infraestrutura) e as tarifas de energia elétrica (visão do consumidor). Os resultados apontam para uma contribuição relevante, em termos de eficiência energética, do emprego de tais tecnologias, representando 35 a 85 MW evitados e redução de emissões de 59 a 145 mil tCO2/ano, dependendo do tipo de modelo residencial adotado, considerando a cidade de São Paulo. A análise de viabilidade econômica por payback simples apontou os seguintes retornos de investimento: 7,2 a 15,5 anos e 2,3 a 7,4 anos para o investidor em infraestrutura e consumidor, respectivamente, dependendo do modelo residencial. Já a análise por Custo da Energia Economizada (CEE) apontou a viabilidade para o consumidor em todos os modelos residenciais, exceto o de tarifa social. Desta forma, o emprego de tais tecnologias pode contribuir de forma importante com a postergação da expansão da matriz energética, resultando em redução de investimentos em expansão e das emissões de CO2 relacionados à geração de energia elétrica, além de poder representar economia na conta de energia dos moradores. / This study aims to develop a methodology to evaluate the utilization impact of the use perception technologies in residential environment in reducing the demand for electricity and CO2 emissions. These technologies are: standby killer, power manager for computers and presence sensor. Initially, residential loads are selected and their data is collected to compose a database that will be used in the analyzes. Each load and load group receives the appropriate technology and then are calculated the avoided consumption and the acquisition investment of the technology. Loads operational profiles (6, 8 and 10h) were created to represent user behaviors and loads usage scenarios (A, B and C) were created to conduct a sensitivity analysis. Case studies were carried out with different residential models, where were calculated: avoided electricity consumption and electric energy demand and CO2 emission reduction (considering a set of similar residences). Also, it was conducted the analysis of economic implantation viability, considering the Expansion Marginal Cost of the electric sector (infrastructure investor view) and the electric energy rates (customer view). The results point out to a relevant contribution, in terms of energy efficiency, of the utilization of such technologies, representing 35 to 85 MW of avoided demand and emission reductions of 59 to 145 thousand tCO2, per year, depending on the residential model type adopted, considering Sao Paulo city region. The analysis of economic implantation viability by payback point out the following investments returns: from 7.2 to 15.5 years and from 2.3 to 7.4 years to infrastructure investor and customer, respectively, depending on the residence model. The analysis by Cost of Saved Energy point out the implementation viability for the costumer in all residential models, except the social tariff. Thus, the use of such technologies can significantly contribute to the postponement of the energetic matrix expansion, resulting in reduction of expansion investments and of CO2 related to electric energy generation, besides can represent savings in the residents energy bill.

Les applications temps réel modernes deviennent plus exigeantes en termes de ressources et de débit amenant la conception d'architectures multiprocesseurs. Ces systèmes, des équipements embarqués au calculateur haute performance, sont, pour des raisons d'autonomie et de fiabilité, confrontés des problèmes cruciaux de consommation d'énergie. Pour ces raisons, cette thèse propose de nouvelles techniques d'optimisation de la consommation d'énergie dans l'ordonnancement de systèmes multiprocesseur. La premiére contribution est un algorithme d'ordonnancement hiérarchique á deux niveaux qui autorise la migration restreinte des tâches. Cet algorithme vise á réduire la sous-optimalité de l'algorithme global EDF. La deuxiéme contribution de cette thèse est une technique de gestion dynamique de la consommation nommée Assertive Dynamic Power Management (AsDPM). Cette technique, qui régit le contrôle d'admission des tâches, vise á exploiter de manière optimale les modes repos des processeurs dans le but de réduire le nombre de processeurs actifs. La troisiéme contribution propose une nouvelle technique, nommée Deterministic Stretch-to-Fit (DSF), permettant d'exploiter le DVFS des processeurs. Les gains énergétiques observés s'approchent des solutions déjà existantes tout en offrant une complexité plus réduite. Ces techniques ont une efficacité variable selon les applications, amenant á définir une approche plus générique de gestion de la consommation appelée Hybrid Power Management (HyPowMan). Cette approche sélectionne, en cours d'exécution, la technique qui répond le mieux aux exigences énergie/performance.

This thesis presents a distributed power-management architecture for concentrating photovoltaic (CPV) systems. Specifically, the Δ-conversion scheme with voltage equalization is analyzed and verified for the CPV system from Morgan Solar, Inc. This architecture uses inverting buck-boost converters, denoted Δ-converters, which equalize the voltages of neighbouring CPV cells in a series-connected string of cells and improve the systems tolerance to parameter variations. The power benefits of Δ-conversion and the Δ-converter current distributions are investigated using statistical simulations. The effectiveness of Δ-conversion in the presence of randomly distributed mismatches is demonstrated, and current cascading is identified as the main design challenge. The Δ-converter is modelled and compensated using Middlebrook's Extra Element Theorem. Analysis of measured data from a six-cell CPV system demonstrate the benefits of Δ-conversion under realistic scenarios. Experimental results from prototype systems show up to 31% power benefits in the presence of mismatches.