Inspired by promotion of commercial applications, support of location-based services to mobile terminals through their current location has been receiving a lot of attention in recent years even though emergency communications is the primary motivation for development of wireless location. A major challenge to wireless location technique is how to balance the implementation complexity and required accuracy. In the first part of this dissertation, we address one of the fundamental problems in wireless location when using the ToA measurements and develop a simple model to estimate the mobile terminal location with low complexity and promising accuracy. The model employs the geometrical transformation method with single propagation delay measurement. The contribution is that the use of geometrical transformation allows us to overcome the location handover problem, i.e., a forcing handover in a GSM (global system for mobile) network or a three-way soft handover in a UMTS (universal mobile telecommunications system) network. By using the proposed location model, the impact on network performance is kept at the minimum level and the complexity and requirements for hardware and software changes are reduced. In the second part of this dissertation, we address one of the fundamental problems in wireless location when using the SS (signal strength) measurements. The first contribution is to develop a novel wireless location technique based on a ¡§differ- encing¡¨ way, called the SSSD (stationary signal-strength-difference), to remove the uncertainty propagation parameters when merging environment-dependent signal propagation model into the location estimation. This is due to the uncertainty in propagation parameters causes a propagation model error that enlarges error in the distance estimation. The performance gained from the preliminary analysis of SSSD location technique, however, is degraded as a result of the large bias error in the estimated distance and distance difference. To achieve the performance enhancement, the second contribution is to correct the bias error in the estimated distance difference by using a correction method based on a geometric constraint condition. With the corrected distance difference, the final contribution is that we generalized the work on correction method and provide a new framework to correct the error in the estimated distance. As the corrected distance and distance difference is derived by LS (least square) computation, respectively, low computation burden and non-iterative solutions were achieved. To the best of our knowledge thus far, this is first such proposal for a correction to the SS-based location technique. It is demonstrated that the proposed error correction method is shown to perform well when encountering the large error in the estimated distance and distance difference, and prove that the location accuracy can be improved considerably.

With the rapid development of wireless communication technology, the demands for higher communication rates are increasing. Higher communication rate corresponds to higher DoF. Interference alignment, which is an emerging interference management technique, is able to substantially increase the DoF of wireless communication systems. This thesis mainly studies the delay-based interference alignment technique. The key problem lies in the design of the transmission scheme and the appropriate allocation of the propagation delay, so as to achieve the desired DoF of different wireless networks. In addition, through delay-based interference alignment, the achievability of extreme points of the DoF region of different wireless networks can be proved.

No description available.

Ortsbasierte Dienste erfreuen sich in den letzten Jahren starker Beliebtheit. Für deren Umsetzung sind sog. Lokalisierungsdienste notwendig, welche eine Ortung von Mobilgeräten erlauben. Das GPS stellt den wohl populärsten Lokalisierungsdienst dar, ist jedoch innerhalb von Gebäuden nur sehr beschränkt einsetzbar. In der Vergangenheit wurden deshalb Methoden vorgeschlagen, die zur Positionsbestimmung auf die Messung der Empfangsfeldstärke von WLAN-Aussendungen zurückgreifen. Im Rahmen der Diplomarbeit soll untersucht werden, ob sich ebenfalls eine Postionsbestimmung anhand von Laufzeiten der WLAN-Signale umsetzen lässt. Bedingung hierbei ist, dass der Lokalisierungsdienst - eine reine Softwarelösung darstellt und keine Modifikationen an Hard- oder Firmware voraussetzt und - die Lokalisierung ohne für diese Zwecke ausgelegte Spezialhardware umsetzbar ist. Diese Anforderungen sollen sicherstellen, dass der zu entwickelnde Lokalisierungsdienst mit bereits installierter, handelsübliche Hardware umsetzbar ist. Es sind in Frage kommende Verfahren zur Bestimmung der Signallaufzeit zu erörtern. Für die Laufzeitmessung in Frage kommenden Zeitquellen sollen zugänglich gemacht und auf ihre Tauglichkeit untersucht werden. Durch Messreihen ist zu untersuchen, ob mit den vorgeschlagenen Messverfahren eine Lokalisierung möglich ist und in welchem Rahmen sich die zu erwartende Genauigkeit bewegt. Die in dieser Arbeit beschriebenen Konzepte sollen im Rahmen einer Proof of Concept Anwendung implementiert werden. Die Software soll unter dem Gesichtspunkt der Wiederverwendbarkeit entwickelt werden, um eine spätere Nutzung im Rahmen anderer Projekte zu ermöglichen.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / A system to generate a contiguous high speed time division multiplexed (TDM) spacecraft downlink data stream has been developed. The 25 MBPS downlink data stream contains high rate real time imager data, intermediate rate subsystem processor data, and low rate spacecraft housekeeping data. Imager data is transferred directly into the appropriate TDM downlink data window using control signals and clocks generated in the central data formatter and distributed to the data sources. Cable and electronics delays inherent in this process can amount to several clock periods, while the uncertainty and variations in those delays (e.g. temperature effects) can exceed the clock period. Unique (patent pending) electronic circuitry has been included in the data formatter to sense the total data gathering delay for each high speed data source and use the results to control series programmable delay elements to equalize the delays from all sources and permit the formation of a contiguous output data stream.

In this thesis, we present a high-speed non-classical unipolar CMOS with a thick sidewall-spacer gate-oxide NMOS load. This unipolar CMOS is composed of a NMOS driver and a thick sidewall-spacer gate-oxide NMOS which replaces a PMOS as load. We focus on the investigation of punch-through current in unipolar CMOS trends. In addition, we also design a conventional CMOS for comparison. According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 20 % compared with the conventional CMOS. This is due to the presence of a thick sidewall-spacer gate-oxide NMOS load. For the viewpoint of device fabrication, the N well process can also be eliminated. This means that the proposed NMOS load not only improves the CMOS speed, but also reduces the fabrication cost. Thus, because of the shared-terminal output, the layout area can be significantly decreased 41 %, in comparison with the conventional CMOS.

This thesis presents ambient energy data obtained from a measurement campaign carried out at an automobile plant. At the automobile plant, ambient light, ambient temperature and ambient radio frequency were measured during the day time over two days. The measurement results showed that ambient light generated the highest DC power. For plant and operation managers at the automobile plant, the measurement data can be used in system design considerations for future energy harvesting wireless sensor nodes at the plant. In addition, wideband measurements obtained from a machine workshop are presented in this thesis. The power delay profile of the wireless channel was obtained by using a frequency domain channel sounding technique. The measurements were compared with an equivalent ray tracing model in order to validate the suitability of the commercial propagation software used in this work. Furthermore, a novel technique for mathematically recreating the time dispersion created by factory inventory in a radio frequency channel is discussed. As a wireless receiver design parameter, delay spread characterizes the amplitude and phase response of the radio channel. In wireless sensor devices, this becomes paramount, as it determines the complexity of the receiver. In reality, it is sometimes difficult to obtain full detail floor plans of factories for deterministic modelling or carry out spot measurements during building construction. As a result, radio provision may be suboptimal. The method presented in this thesis is based on 3-D fractal geometry. By employing the fractal overlaying algorithm presented, metallic objects can be placed on a floor plan so as to obtain similar radio frequency channel effects. The environment created using the fractal approach was used to estimate the amount of energy a harvesting device can accumulate in a University machine workshop space.

Este trabalho visa propor uma metodologia de análise da variabilidade do tempo de atraso de propagação no FPGA. Para alcançar esse objetivo são utilizados três circuitos diferentes: o circuito 1 mede a diferença de atrasos de dois circuitos, o circuito 2 identifica o atraso menor de dois circuitos e, por fim, o terceiro circuito que consiste do oscilador em anel. Cada circuito foi avaliado individualmente numa estrutura BIST, implementada nos FPGA XC3S200-FT256 e EP2C35F672C6. Os métodos utilizados para análise dos dados foram a média móvel, o plano de mínimos quadrados e o teste t-student. A metodologia permitiu mostrar a variabilidade within-die e suas componentes sistêmica e randômica. / This work aims to propose a methodology of analysis of variability of propagation-delay time in FPGA. To achieve this goal three different circuits are implemented: the circuit 1 measures the delay difference of two logic paths, the circuit 2 identifies smallest delay of two logic paths, and finally the third circuit consists of a ring oscillator. Each circuit has been assessed individually in a BIST structure, implemented in FPGAs XC3S200-FT256 and EP2C35F672C6. The methods used for data analysis were the moving average, least-squares plane and the t-student test. The methodology has allowed to evaluate the within-die variability and its systemic and random components.

Este trabalho visa propor uma metodologia de análise da variabilidade do tempo de atraso de propagação no FPGA. Para alcançar esse objetivo são utilizados três circuitos diferentes: o circuito 1 mede a diferença de atrasos de dois circuitos, o circuito 2 identifica o atraso menor de dois circuitos e, por fim, o terceiro circuito que consiste do oscilador em anel. Cada circuito foi avaliado individualmente numa estrutura BIST, implementada nos FPGA XC3S200-FT256 e EP2C35F672C6. Os métodos utilizados para análise dos dados foram a média móvel, o plano de mínimos quadrados e o teste t-student. A metodologia permitiu mostrar a variabilidade within-die e suas componentes sistêmica e randômica. / This work aims to propose a methodology of analysis of variability of propagation-delay time in FPGA. To achieve this goal three different circuits are implemented: the circuit 1 measures the delay difference of two logic paths, the circuit 2 identifies smallest delay of two logic paths, and finally the third circuit consists of a ring oscillator. Each circuit has been assessed individually in a BIST structure, implemented in FPGAs XC3S200-FT256 and EP2C35F672C6. The methods used for data analysis were the moving average, least-squares plane and the t-student test. The methodology has allowed to evaluate the within-die variability and its systemic and random components.

Este trabalho visa propor uma metodologia de análise da variabilidade do tempo de atraso de propagação no FPGA. Para alcançar esse objetivo são utilizados três circuitos diferentes: o circuito 1 mede a diferença de atrasos de dois circuitos, o circuito 2 identifica o atraso menor de dois circuitos e, por fim, o terceiro circuito que consiste do oscilador em anel. Cada circuito foi avaliado individualmente numa estrutura BIST, implementada nos FPGA XC3S200-FT256 e EP2C35F672C6. Os métodos utilizados para análise dos dados foram a média móvel, o plano de mínimos quadrados e o teste t-student. A metodologia permitiu mostrar a variabilidade within-die e suas componentes sistêmica e randômica. / This work aims to propose a methodology of analysis of variability of propagation-delay time in FPGA. To achieve this goal three different circuits are implemented: the circuit 1 measures the delay difference of two logic paths, the circuit 2 identifies smallest delay of two logic paths, and finally the third circuit consists of a ring oscillator. Each circuit has been assessed individually in a BIST structure, implemented in FPGAs XC3S200-FT256 and EP2C35F672C6. The methods used for data analysis were the moving average, least-squares plane and the t-student test. The methodology has allowed to evaluate the within-die variability and its systemic and random components.