CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Neste trabalho, apresentamos uma anÃlise numÃrica para a obtenÃÃo de portas lÃgicas totalmente Ãptica baseada em um acoplador direcional nÃo-linear simÃtrico (NLDC) em fibras de cristal fotÃnico (PCF). O projeto mais comumente usado para o NLDC-PCF à uma fibra holey, utilizada neste trabalho, em que a seÃÃo transversal à uma matriz periÃdica de buracos de ar que se prolonga por todo o comprimento da fibra, operando com dois pulsos de luz ultracurtos na forma de sÃlitons, de duraÃÃo mÃnima de 100fs (femtosegundos). Investigamos dois formatos de modulaÃÃo por pulsos, a modulaÃÃo por amplitude de pulso (PAM) na modalidade de chaveamento de mudanÃa de amplitude (ASK) e a modulaÃÃo por largura de pulso (PWM) para obter portas lÃgicas no NLDC-PCF duplo simÃtrico. Avaliamos o efeito resultante de um incremento no parÃmetro codificaÃÃo PAM (ε) e PWM (w), considerando a dispersÃo de segunda ordem (β2), a dispersÃo de terceira ordem (β3) e efeitos nÃo-lineares, tais como: SPM (Self Phase Modulation), SS (Self-Steepening) e IRS (lntrapulse Raman Scattering) em uma configuraÃÃo sem perdas. Os nossos resultados indicam que à possÃvel obter operaÃÃes lÃgicas utilizando um controle de fase entre os pulsos de entrada. / We present a numerical analysis for obtaining all-optical logic gates based on a nonlinear directional coupler symmetric (NLDC) based on photonic crystal fibers (PCF). The most commonly used to project the NLDC-PCF is a holey fiber, used here in cross section which is a periodic array of air holes extending through the length of the fiber, using two ultrashort light pulses in form of solitons, the minimum duration of 100fs (femtoseconds). We investigated two forms of modulation pulse, pulse amplitude modulation (PAM) in the form of amplitude shift keying (ASK) modulation and pulse width modulation (PWM) for logic gate NLDC-PCF symmetrical double. We evaluated the effect resulting from an increase in the offset parameter encoding PAM (ε) and PWM (w), considering the second order dispersion (β2), the third order dispersion (β3) and non-linear modulation effects SPM (Self Phase Modulation), SS (Self-Steepening) and IRS (lntrapulse Raman Scattering) in a configuration without loss. Our results indicate that logical operations can be obtained using a phase control between the input pulses.

<p>Shift-by-Wire is about replacing the mechanical link between the automatic transmission and the shift lever with an electromechanical system. This will make new safety functions possible and assist the driver in other ways. </p><p>To do this, an actuator with a brushless DC motor is built into the transmission. It controls the position of the shift valve, which decides the driving position. </p><p>This thesis concerns the controlling of the brushless DC motor. This is done by programming a shift control unit with a Motorola HC12 microcontroller. The performance of the motor is then tested and evaluated.</p>

AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.

Shift-by-Wire is about replacing the mechanical link between the automatic transmission and the shift lever with an electromechanical system. This will make new safety functions possible and assist the driver in other ways. To do this, an actuator with a brushless DC motor is built into the transmission. It controls the position of the shift valve, which decides the driving position. This thesis concerns the controlling of the brushless DC motor. This is done by programming a shift control unit with a Motorola HC12 microcontroller. The performance of the motor is then tested and evaluated.

This research work is devoted to the analysis, design and development of the Current-Source Converter (CSC) based distribution-type Static Synchronous Compensator (D-STATCOM) for low-voltage applications in reactive-power control in order to achieve i) faster transient response in reactive-power control, ii) lower current harmonic distortion, iii) lower power losses and iv) minimum storage elements in comparison with conventional solutions. The developed CSC-D-STATCOM includes a low-pass input filter and a three phase forced-commutated CSC which is composed of six insulated gate bipolar transistors (IGBT) with built-in series diodes. The analysis and the control of the CSC-D-STATCOM are carried out in dq-synchronous reference frame in order to obtain the reference current waveform which is to be generated by switching the IGBTs at 3kHz with the use of space vector modulation.

AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.

In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²). / text

In this thesis, a new approach for single-stage power factor correction converters is proposed to increase their power ratings to be in the multiple kilowatts levels. The proposed techniques are based on the utilization of modified three-level resonant converter topologies. These topologies provide low component stresses, high frequency operation, zero voltage switching, applicability under a wide range of input and output conditions as well as added control flexibility. The proposed control algorithms are based on a combination of variable frequency and asymmetrical pulse width modulation control or variable frequency and phase shift modulation control. In either case, the variable frequency control is used to tightly regulate the output voltage, whereas, pulse width or phase shift modulation is used to regulate the dc-bus voltage as well as the input power factor. New converter topologies, their operation and steady state and dynamic analyses are presented in details. A modelling approach based on average multiple frequency methods is also proposed. This approach leads to the development of a full order state space model with the two control variables explicitly separated allowing a better controller design. The model can be used either at high level of detail expressing the non-linearities of the system or it can readily be simplified to a linear decoupled model for approximate solutions. Finally, a discrete time controller for the proposed converters, which is suitable for FPGA implementation, is presented. Analytical, simulation and experimental results are provided to verify the proposed concepts. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-01-30 14:28:15.725

Power electronic systems have been widely used in the electrical power processing for applications with power levels ranging from less than one watt in battery-operated portable devices to more than megawatts in the converters, inverters and rectifiers of the utility power systems. These systems typically involve the passive elements such as inductors, capacitors, and resistors, the switching electronic components such as IGBTs, MOSFETS, and diodes, and other electronic circuits. Multifrequency averaging is one of the widely used modeling and simulation techniques today for the analysis and design of power electronic systems. This technique is capable of providing the average behavior as well as the ripple behavior of power electronic systems. This work begins with the extension of multifrequency averaging to represent uniformly sampled PWM converters. A new multifrequency averaging method of solving an observed issue with model stability is proposed and validated. Multifrequency averaging can also be applied to study the instability phenomenon in power electronic systems. In particular, a reduced-order multifrequency averaging method, along with a genetic algorithm based procedure, is proposed in this work to estimate the regions of attraction of power electronic converters. The performance of this method is shown by comparing the accuracy and efficiency with the existing methods. Finally, a new continuous-time multifrequency averaging method of representing discrete-time systems is proposed. The proposed method is applied to model digitally controlled PWM converters. Simulation and hardware results show that the proposed method is capable of predicting the average behavior as well as the ripple behavior of the closed-loop systems. Future research in the area of multifrequency averaging is proposed.

This thesis deals with the design and implementation of a feedback control scheme for a DC Hybrid Active Power Filter used to filter harmonics from a Switched Reluctance Motor (SRM) Drive load. Power electronic systems are non-linear & dynamic [1,3,5]. Power electronic systems employ switching circuits to maximize their efficiency at the penalty that switching circuits generate electrical noise called ripple current and voltage or conducted electromagnetic interference (EMI). The ripple current drawn by the power electronic systems needs to be attenuated to an acceptable level. Filters attenuate this to an acceptable level. Traditionally filters with passive inductors and capacitors are used. Active filters contain switching elements in addition to passive inductors and capacitors which reduce overall size of passive components used. Two control approaches, full-state state space, and plain proportional feedback, are evaluated for this filter. Circuit models are simulated in SPICE and mathematical models are simulated in Matlab/Simulink for evaluating these control approaches. Proportional feedback control was chosen for implementation and the reason for this is provided in the thesis. The active filter was tested with chosen feedback control and experimental results were compared with simulation results. Inferences and scope for further work are finally presented.