This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.

This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.

Les communications numériques ont évolué pour répondre à la demande des consommateurs pour accroître l'accès à la navigation Internet, TV, vidéo à la demande, jeux interactifs et de réseaux sociaux. Cette augmentation de débit est obtenue en utilisant des techniques avancées de traitement du signal, des modulations complexes, et des bandes passantes larges. Par conséquent, des récepteurs hautes performances, capables de traiter des signaux large bande, sont nécessaires pour les équipements d'infrastructure et de communication grand-public hauts de gamme. Les récepteurs à numérisation directe RF sont attrayants pour ces applications à large bande, mais plusieurs aspects doivent être étudiés afin de fournir des solutions performantes intégrées. Les principales contributions de cette thèse sont les suivantes: - l’analyse et la conception au niveau système des récepteurs à échantillonnage et numérisation directs RF : - l'analyse théorique de la distorsion non-linéaire large-bande, pour les stratégies d'échantillonnage passe-bas et passe-bande - l'analyse théorique des défauts des convertisseurs analogique-numérique haute-vitesse dans un contexte de réception large bande - la conception d'un conditionneur de signal RF optimisé pour une application câble, incluant: - un égaliseur RF programmable multi-pente, utilisant une seule inductance, avec son algorithme de contrôle - une boucle de contrôle de gain mixte combinant un détecteur RMS et un détecteur crête - contribution à la réalisation d'un produit récepteur RF multi-canaux, à numérisation directe, compétitif en consommation d'énergie, coût, et performances RF / The Holy Grail radio receiver architecture for Software Radio makes uses of direct RF digitization. The early RF signal digitization theoretically provides maximum re-configurability of the radio front-end to multiple bands and standards, as opposed to analog-extensive front-ends. In addition, in applications for which a large portion of the RF input signal spectrum is required to be received simultaneously, the RF direct digitization architecture could provide the most power-and-cost-effective front-end solution. This is typically the case in centralized architectures, for which a single receiver is used in a multi-user environment (data and video gateways) or in re-multiplexing systems. In these situations, this highly-digitized architecture could dramatically simplify the radio front-end, as it has the potential to replace most of the analog processing. In this Ph.D thesis, we study the trade-offs, from RF to DSP domains, which are being involved in direct RF digitization receivers. The developed system-level framework is applied to the design of a cable multi-channel RF direct digitization receiver. Special focus is provided on the design of an optimum RF signal conditioning, on the specification of time-interleaved analog-to-digital converter impairments, including clock quality, and on some algorithmic aspects (automatic gain control loop, RF front-end amplitude equalization control loop). The two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. The solution is highly competitive, both in terms of area and RF performance, while it drastically reduces power consumption.

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This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

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