Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy particle from such an environment may cause voltage/current transients, thereby inducing Single Event Effect (SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975, this community has made tremendous progress in investigating the mechanisms of SEE and exploring radiation tolerant techniques. However, as the IC technology advances, the existing hardening techniques have been rendered less effective because of the reduced spacing and charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has identified radiation-induced soft errors as the major threat to the reliable operation of electronic systems in the future. In digital systems, hardening techniques of their core components, such as latches, logic, and clock network, need to be addressed. Two single event tolerant latch designs taking advantage of feedback transistors are presented and evaluated in both single event resilience and overhead. These feedback transistors are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in a larger feedback delay and higher single event tolerance. On the other hand, these extra transistors are turned ON when the cell is in the write mode. As a result, no significant write delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section when compared to the reference cells. Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The worst case occurs when the output is evaluated logic high, where the pull-up networks are turned OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail. A capacitor added to the feedback path increases the node capacitance of the output and the feedback delay, thereby increasing the single event critical charge. Another differential structure that has two differential inputs and outputs eliminates single event upset issues at the expense of an increased number of transistors. Clock networks in advanced technology nodes may cause significant errors in an IC as the devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme in a digital system. It was fabricated in a 28nm technology and evaluated through the use of heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was demonstrated during these tests. In addition to mitigating single event issues by using hardened designs, built-in current sensors can be used to detect single event induced currents in the n-well and, if implemented, subsequently execute fault correction actions. These sensors were simulated and fabricated in a 28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of this sensor design. This manifests itself as an alternative to existing hardening techniques. In conclusion, this work investigates single event effects in digital systems, especially those in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock, and current sensor designs have been presented and evaluated. Through the use of these designs, the single event tolerance of a digital system can be achieved at the expense of varying overhead in terms of area, power, and delay.

The aim with this thesis has been to make a survey of radiation hardened electronics, explaining why and how radiation affects electronics and what can be done to harden it. The effects radiation have on electronics in general and in specific commonly used devices are explained qualitatively. The effects are divided into Displacement Damage (DD), Total Ionizing Dose (TID) and Single Event Effects (SEEs). The devices explained are MOSFETs, Silicon On Insulator (SOI) transistors, 3D-transistors, Power transistors, Optocouplers, Field Programmable Gate Arrays (FPGAs), three dimensional circuits (3D-ICs) and Flash memories. Different radiation hardening by design (RHBD) techniques used to reduce or to remove the negative effects radiation induces in electronics are also explained. The techniques are Annular transistors, Enclosed source/drain transistors, Guard rings, Triple Modular Redundancy (TMR), Dual Interlocked Storage Cells (DICE), Guard gates, Temporal filtering,Multiple drive, Charge dissipation, Differential Charge Cancellation (DCC), Scrubbing, Lockstep, EDAC codes and Watchdog timers.

abstract: Implantable medical device technology is commonly used by doctors for disease management, aiding to improve patient quality of life. However, it is possible for these devices to be exposed to ionizing radiation during various medical therapeutic and diagnostic activities while implanted. This commands that these devices remain fully operational during, and long after, radiation exposure. Many implantable medical devices employ standard commercial complementary metal-oxide-semiconductor (CMOS) processes for integrated circuit (IC) development, which have been shown to degrade with radiation exposure. This necessitates that device manufacturers study the effects of ionizing radiation on their products, and work to mitigate those effects to maintain a high standard of reliability. Mitigation can be completed through targeted radiation hardening by design (RHBD) techniques as not to infringe on the device operational specifications. This thesis details a complete radiation analysis methodology that can be implemented to examine the effects of ionizing radiation on an IC as part of RHBD efforts. The methodology is put into practice to determine the failure mechanism in a charge pump circuit, common in many of today's implantable pacemaker designs, as a case study. Charge pump irradiation data shows a reduction of circuit output voltage with applied dose. Through testing of individual test devices, the response is identified as parasitic inter-device leakage caused by trapped oxide charge buildup in the isolation oxides. A library of compact models is generated to represent isolation oxide parasitics based on test structure data along with 2-Dimensional structure simulation results. The original charge pump schematic is then back-annotated with transistors representative of the parasitic. Inclusion of the parasitic devices in schematic allows for simulation of the entire circuit, accounting for possible parasitic devices activated by radiation exposure. By selecting a compact model for the parasitics generated at a specific dose, the compete circuit response is then simulated at the defined dose. The reduction of circuit output voltage with dose is then re-created in a radiation-enabled simulation validating the analysis methodology. / Dissertation/Thesis / M.S. Electrical Engineering 2010

Neste trabalho foi elaborado um microcontrolador 8051 tolerante à radiação, usando para isso técnicas de recomputação de instruções. A base para este trabalho foi a descrição VHDL desse microcontrolador, sendo proposto o uso de sensores de radiação, Bulk-BICS, e códigos de proteção de erros para os elementos de memória, como forma de suporte à técnica apresentada. Inicialmente serão abordados sucintamente a origem e os efeitos prejudiciais da radiação nos dispositivos eletrônicos, motivando a realização deste trabalho. Serão mostrados em detalhes os passos para implementar a técnica de recomputação, que consiste em monitorar os sensores e, ao ser detectado um pulso transiente, fazer o processador reler a última instrução e executá-la novamente, a fim de mitigar o efeito do SET (Single Event Transient). Para isso a manipulação do contador de programa (PC) e o apontador de pilha (SP) são fundamentais. Durante esse processo também deve ser garantido que nenhum dado, potencialmente corrompido, seja armazenado na memória. Contra SEUs (Single Event Upsets) é pressuposto que todos os elementos de memória do microcontrolador estão protegidos através de algum código de correção de erros, assunto já pesquisado por outros autores. Na seqüência serão apresentadas várias simulações realizadas, onde é possível ver o processo de recomputação sendo iniciado a partir da incidência de partículas geradas através de um testbench. Por fim será feita uma comparação entre o 8051 original e o protegido, mostrando dados de área, freqüência de operação e potência de cada um. / This work presents a radiation hard 8051 microcontroller, designed using instruction recomputation techniques. The basis for this work was the VHDL description of the microcontroller. To make the microcontroller radiation hard, built in radiation sensors, called Bulk-BICS, were use to protect the combinational logic blocks. Codes for error detection and correction were used to protect the memory elements. Initially, this work discusses the sources of ionizing radiation and its harmful effects on digital integrated circuits, showing the motivation for this work. Next, the details of the implemented instruction re-computation technique are shown. It consists in monitoring the radiation sensors and, if the incidence of ionizing radiation is detected, the processor reads the last instruction and executes it again, in order to mitigate the effect of a single event transient (SET). In order to implement this re-computation, the manipulation of the program counter (PC) and stack pointer (SP) is essential. During this process it must be guaranteed that any data, potentially corrupted, will not be stored in memory. Regarding radiation effects on memory elements (Single Event Upsets-SEUs), it is assumed that all memory elements of the microcontroller are protected by some error detection and correction code, a topic previously studied by other authors. Finally, several simulations will be shown, where it is possible to see the evolution of the re-computation process, from the detection of the incidence of ionizing radiation (incidence generated by a testbench) to the full re-computation of the instruction. Finally, a comparison is made between the performance of the original 8051 and the radiation hardened version, showing overheads of area, frequency of operation and power.

Neste trabalho foi elaborado um microcontrolador 8051 tolerante à radiação, usando para isso técnicas de recomputação de instruções. A base para este trabalho foi a descrição VHDL desse microcontrolador, sendo proposto o uso de sensores de radiação, Bulk-BICS, e códigos de proteção de erros para os elementos de memória, como forma de suporte à técnica apresentada. Inicialmente serão abordados sucintamente a origem e os efeitos prejudiciais da radiação nos dispositivos eletrônicos, motivando a realização deste trabalho. Serão mostrados em detalhes os passos para implementar a técnica de recomputação, que consiste em monitorar os sensores e, ao ser detectado um pulso transiente, fazer o processador reler a última instrução e executá-la novamente, a fim de mitigar o efeito do SET (Single Event Transient). Para isso a manipulação do contador de programa (PC) e o apontador de pilha (SP) são fundamentais. Durante esse processo também deve ser garantido que nenhum dado, potencialmente corrompido, seja armazenado na memória. Contra SEUs (Single Event Upsets) é pressuposto que todos os elementos de memória do microcontrolador estão protegidos através de algum código de correção de erros, assunto já pesquisado por outros autores. Na seqüência serão apresentadas várias simulações realizadas, onde é possível ver o processo de recomputação sendo iniciado a partir da incidência de partículas geradas através de um testbench. Por fim será feita uma comparação entre o 8051 original e o protegido, mostrando dados de área, freqüência de operação e potência de cada um. / This work presents a radiation hard 8051 microcontroller, designed using instruction recomputation techniques. The basis for this work was the VHDL description of the microcontroller. To make the microcontroller radiation hard, built in radiation sensors, called Bulk-BICS, were use to protect the combinational logic blocks. Codes for error detection and correction were used to protect the memory elements. Initially, this work discusses the sources of ionizing radiation and its harmful effects on digital integrated circuits, showing the motivation for this work. Next, the details of the implemented instruction re-computation technique are shown. It consists in monitoring the radiation sensors and, if the incidence of ionizing radiation is detected, the processor reads the last instruction and executes it again, in order to mitigate the effect of a single event transient (SET). In order to implement this re-computation, the manipulation of the program counter (PC) and stack pointer (SP) is essential. During this process it must be guaranteed that any data, potentially corrupted, will not be stored in memory. Regarding radiation effects on memory elements (Single Event Upsets-SEUs), it is assumed that all memory elements of the microcontroller are protected by some error detection and correction code, a topic previously studied by other authors. Finally, several simulations will be shown, where it is possible to see the evolution of the re-computation process, from the detection of the incidence of ionizing radiation (incidence generated by a testbench) to the full re-computation of the instruction. Finally, a comparison is made between the performance of the original 8051 and the radiation hardened version, showing overheads of area, frequency of operation and power.

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Neste trabalho foi elaborado um microcontrolador 8051 tolerante à radiação, usando para isso técnicas de recomputação de instruções. A base para este trabalho foi a descrição VHDL desse microcontrolador, sendo proposto o uso de sensores de radiação, Bulk-BICS, e códigos de proteção de erros para os elementos de memória, como forma de suporte à técnica apresentada. Inicialmente serão abordados sucintamente a origem e os efeitos prejudiciais da radiação nos dispositivos eletrônicos, motivando a realização deste trabalho. Serão mostrados em detalhes os passos para implementar a técnica de recomputação, que consiste em monitorar os sensores e, ao ser detectado um pulso transiente, fazer o processador reler a última instrução e executá-la novamente, a fim de mitigar o efeito do SET (Single Event Transient). Para isso a manipulação do contador de programa (PC) e o apontador de pilha (SP) são fundamentais. Durante esse processo também deve ser garantido que nenhum dado, potencialmente corrompido, seja armazenado na memória. Contra SEUs (Single Event Upsets) é pressuposto que todos os elementos de memória do microcontrolador estão protegidos através de algum código de correção de erros, assunto já pesquisado por outros autores. Na seqüência serão apresentadas várias simulações realizadas, onde é possível ver o processo de recomputação sendo iniciado a partir da incidência de partículas geradas através de um testbench. Por fim será feita uma comparação entre o 8051 original e o protegido, mostrando dados de área, freqüência de operação e potência de cada um. / This work presents a radiation hard 8051 microcontroller, designed using instruction recomputation techniques. The basis for this work was the VHDL description of the microcontroller. To make the microcontroller radiation hard, built in radiation sensors, called Bulk-BICS, were use to protect the combinational logic blocks. Codes for error detection and correction were used to protect the memory elements. Initially, this work discusses the sources of ionizing radiation and its harmful effects on digital integrated circuits, showing the motivation for this work. Next, the details of the implemented instruction re-computation technique are shown. It consists in monitoring the radiation sensors and, if the incidence of ionizing radiation is detected, the processor reads the last instruction and executes it again, in order to mitigate the effect of a single event transient (SET). In order to implement this re-computation, the manipulation of the program counter (PC) and stack pointer (SP) is essential. During this process it must be guaranteed that any data, potentially corrupted, will not be stored in memory. Regarding radiation effects on memory elements (Single Event Upsets-SEUs), it is assumed that all memory elements of the microcontroller are protected by some error detection and correction code, a topic previously studied by other authors. Finally, several simulations will be shown, where it is possible to see the evolution of the re-computation process, from the detection of the incidence of ionizing radiation (incidence generated by a testbench) to the full re-computation of the instruction. Finally, a comparison is made between the performance of the original 8051 and the radiation hardened version, showing overheads of area, frequency of operation and power.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

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