­^¤åºK­n¡G In this thesis, a two-step de-embedded techniques was applied to measure the important parameters, ft and fmax , of the heterojunction bipolar transistors(HBTs). The same technique was also used to measure the wide-band S parameters for modeling and evaluating the bump chip carrier(BCC) packages. In the simulation, the Ansoft HFSS simulator was used to calculate the insertion and return losses for some bare and packaged test chips. Comparison between simulated and measured results has been discussed in detail to illustrate the applicability of the HFSS simulator.

The ultimate goal of the modern wireless communication industry is the full integration of digital, analog, and radio frequency (RF) functions. The most successful solution for such demands has been complementary metal oxide semiconductor (CMOS) technology, thanks to its cost-effective material and great versatility. Power amplifier (PA), the biggest bottleneck to integrate in a single-chip transceiver in wireless communications, significantly influences overall system performance. Recent advanced wireless communication systems demand a power amplifier that can simultaneously support different communication standards. A fully integrated single-chip tunable CMOS power amplifier is the best solution in terms of the cost and level of integration with other functional blocks of an RF transceiver. This work, for the first time, proposes a fully integrated band-switchable RF power amplifier by using a novel approach towards switching the matching networks. In this approach, which is called Bit Optimized Reconfigurable Network (BORN), two matching networks which can be controlled by digital bits will provide three operating frequency bands for the power amplifier. In order to implementing the proposed BORN PA, a robust high-power RF switch is presented by using resistive body floating technique and 6-terminal triple-well NMOS. The proposed BORN PA delivers measured saturated output power (Psat) of 21.25/22.25/ 23.0dBm at 960MHz/1317MHz/1750MHz, respectively. Moreover, the proposed BORN PA provides respective 3-dB bandwidth of 400MHz/425MHz/550MHz, output 1-dB compression point (P1dB) of 19.5dBm/20.0dBm/21.0dBm, and power-added efficiency (PAE) of 9/11/13% at three targeted frequency bands, respectively. The promising results show that the proposed BORN PA can be a practical solution for RF multiband applications in terms of the cost and level of integration with other functional blocks of an RF transceiver.

CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range of 3 GHz to 10 GHz, which is not feasible for existing CMOS analog-to-digital converters. In this dissertation, we investigate the two technical challenges at the circuit level and the system level. We propose a systematic approach at the circuit level for optimal transistor sizing and biasing conditions that result in optimal noise and power matching over a wide bandwidth. We also propose a general scheme for wideband matching. To verify our methods, we design two single-stage low noise amplifiers (LNAs) in TSMC 0.18µm CMOS technology. Measurement results from fabricated chips indicate that the proposed LNAs could achieve as high as 16 dB power gain and as low as 2.2 dB noise figure with only 6.4 mA current dissipation under a supply voltage of 1.2 V. At the system level, we propose a unique frequency domain receiver architecture. The receiver samples frequency components of a received signal rather than the traditional approach of sampling a received signal at discrete instances in time. The frequency domain sampling leads to a simple RF front-end architecture that directly samples an RF signal without the need to downconvert it into a baseband signal. Further, our approach significantly reduces the sampling rate to the pulse repetition rate. We investigate a simple, low-power implementation of the frequency domain sampler with 1-bit ADCs. Simulation results show that the proposed frequency-domain UWB receiver significantly outperforms a conventional analog correlator. A digital UWB receiver can be implemented efficiently in CMOS with the proposed LNA as an RF front-end, followed by the frequency domain sampler. / Ph. D.

<p>This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW</p>

This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW

This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed. In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs. We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.

No description available.

Ce travail de thèse s’inscrit dans le cadre d’un projet Français « VéLo » qui est une collaboration entre l’industriel STMicroelectronics et plusieurs laboratoires dont les laboratoires IMS-bordeaux et LAAS. Le but du projet est de concevoir un prototype de radar anticollision millimétrique. Dans ce travail un synthétiseur de fréquence est implémenté. Ce dernier sera intégré dans la chaine de réception du démonstrateur. Une étude bibliographique des architectures classiques de système de radiocommunication a été réalisée. Des exemples d’architectures rencontrées dans le domaine millimétrique ont été étudiés.L’objet principal de cette thèse est l’étude des oscillateurs synchronisés par injection ILO. L’objectif est de réaliser un oscillateur verrouillé par injection qui sera piloté par un oscillateur de fréquence plus basse possédant des caractéristiques de stabilité et de bruit meilleures.Dans ce travail de thèse, le mécanisme de verrouillage des oscillateurs par injection a été décrit. Un modèle de synchronisation par injection série, basé sur la théorie de Huntoon Weiss et inspiré du travail de Badets réalisé sur les oscillateurs synchrones verrouillés par injection parallèle, est proposé. La théorie établie a permis d’exprimer la plage de synchronisation en fonction de la topologie utilisée et des composants de la structure. La validité de la théorie a été évaluée par la simulation de la structure. Les résultats présentés montrent une bonne concordance entre la simulation et la théorie et permettent de valider le principe de synchronisation par injection. La faisabilité de l’intégration d’un ILO millimétrique synchronisé par l’harmonique d’un signal de référence de fréquence plus basse a été démontrée expérimentalement. Le synthétiseur de fréquence est réalisé en technologie BiCMOS 130nm pour des applications millimétriques de STMicroelectronics. Ce dernier opère dans une plage de 2GHz autour de la fréquence 82,5GHz. Les performances en bruit du synthétiseur sont satisfaisantes. Le bruit de phase de l’ILO recopie celui du signal injecté. Les équipements de mesures utilisés, le bruit de phase de l’oscillateur atteint des valeurs inférieures à -110dBc/Hz à 1MHz de la porteuse. / This thesis is a part of a French project "VELO". The project is collaboration between STMicroelectronics and several laboratories including IMS-Bordeaux and LAAS laboratories. The aim of this project is to achieve a prototype of millimeter anti-collision radar. In this work a frequency synthesizer is implemented. This circuit will be incorporated in the reception chain of the demonstrator. A bibliographical study of classical architecture was completed. Examples of architectures encountered in the millimeter frequency range have been studied. The purpose of this thesis is to study the phenomena of synchronization in oscillators. The objective is to design an injection locked oscillator ILO driven by another oscillator, the second oscillator operates at lower frequency and offers better stability and noise characteristics.In this thesis, the injection locking mechanism of the oscillators has been described. A model of synchronization by series injection is proposed. The model is based on the theory of Huntoon and Weiss and inspired by Badets’ work performed on parallel injection. The theory expresses the synchronized frequency range depending on the used topology and the values of the components. The validity of the theory was evaluated by simulation. The results show good agreement between simulation and theory and validate the principle of synchronization by injection.The feasibility of a millimeter ILO synchronized by the harmonic of a reference signal operating at lower frequency has been demonstrated experimentally. The synthesizer was implemented in BiCMOS technology for 130nm applications millimeter of STMicroelectronics. The oscillator operates at 82.5 GHz and performs a frequency range of 2GHz. The noise performance of the synthesizer is satisfactory. The phase noise of the ILO depends on the reference phase noise, and reaches values of -110dBc/Hz at 1MHz from the carrier frequency.