Temperature is a ubiquitous force influencing biological processes ranging from cellular responses to life span. The thermal environment for many organisms is predicted to change with globally increasing temperatures and studies conducted in natural systems incorporating various evolutionary forces, such as gene flow, is needed. In my thesis, I investigate how snails (Radix balthica) originating from distinct geothermal environments within Lake Mývatn in northern Iceland have adapted, both genetically and phenotypically, to the respective thermal regime. Locations were classified as either cold, warm or seasonal depending on the average and variance in temperature. A high resolution spatial distribution of genetic variation within Mývatn was obtained using both neutral and outlier AFLPs. In addition, the genetic profile enabled me identify warm origin snails irrespective of geographic location in Iceland. Warm environments were often more stressful than cold or seasonal environments but snails originating from a high temperature location benefited from increased performance elsewhere. Patterns of growth were identical in both common garden and reciprocal transplant experiment; warm origin snails grew faster than both cold and seasonal origin snails. This result is in concordance with quantitative genetics models of thermal adaptation but suggesting cogradient rather than countergradient variation. Although warm origin snails generally had superior performance, survival at cold temperatures (< 12 °C) was reduced. All snails matured at similar size in the common garden experiment but cold origin snails were observed to mature later and lay fewer eggs. Also, snails had a common optimum for growth rate at 20 °C irrespective of thermal origin. This is arguably the reason why snails were observed to have a common thermal preference. Interestingly, warm origin snails had a reduced tolerance to high temperatures compared to cold and seasonal origin snails which did not differ in tolerance. Putatively, natural selection has reduced a putatively unnecessary trait (high temperature tolerance in a stable thermal environment) in favour of higher growth rate and performance in warm habitats. In conclusion, the price of high performance in a warm environment was paid in terms of reduced survival at low temperatures and a potential disadvantage of reduced genetic variability.

We explore efficient parallel radix sort for the AMD Fusion Accelerated Processing Unit (APU). Two challenges arise: efficiently partitioning data between the CPU and GPU and the allocation of data in memory regions. Our coarse-grained implementation utilizes both the GPU and CPU by sharing data at the begining and end of the sort. Our fine-grained implementation utilizes the APU’s integrated memory system to share data throughout the sort. Both these implementations outperform the current state of the art GPU radix sort from NVIDIA. We therefore demonstrate that the CPU can be efficiently used to speed up radix sort on the APU. Our fine-grained implementation slightly outperforms our coarse-grained implementation. This demonstrates the benefit of the APU’s integrated architecture. This performance benefit is hindered by limitations in the APU’s architecture and programming model. We believe that the performance benefits will increase once these limitations are addressed in future generations of the APU.

Para beneficiarse de una reducción en la latencia así como disminuir tanto el consumo como el coste, el número óptimo de puertos de un conmutador ha ido aumentando a lo largo del tiempo. Sin embargo, las arquitecturas tradicionales se han quedado atrás bien por bajo rendimiento o bien por problemas de escalabilidad con el número de puertos. En esta Tesis se propone una nueva arquitectura de conmutador válida para conmutadores de elevado grado llamada Partitioned Crossbar Input Queued (PCIQ). Esta arquitectura resuelve el problema de los excesivos requerimientos de memoria en el diseño de arquitecturas de elevado grado. Además PCIQ define una nueva familia de arquitecturas de conmutador. PCIQ se basa en un particionado inteligente del crossbar, dividiéndolo en sub-crossbars, requiriendo menos recursos de memoria que las otras propuestas para conmutadores de elevado grado y que consigue una mayor eficiencia debido en parte a un incremento en la eficiencia de los árbitros empleados en el diseño. En este sentido, PCIQ emplea dos árbitros con prioridad rotativa (uno para cada sub-crossbar) que presentan un coste lineal y una respuesta en el tiempo logarítmica conforme aumenta el número de puertos del conmutador. Además PCIQ tiene un coste (medido en términos de requerimientos de memoria, complejidad del crossbar y complejidad en el arbitraje) similar o incluso menor que organizaciones básicas como CIOQ. No obstante PCIQ es capaz de conseguir máxima eficiencia para distribuciones de tráfico uniforme. El bloqueo por paquete al principio de cola (o HOL en inglés) reduce dramáticamente el rendimiento del conmutador. Las soluciones tradicionales para eliminar el bloqueo por HOL no son escalables con el número de puertos o requieren arquitecturas complejas. En esta Tesis se propone una técnica de control de la congestión que elimina el bloqueo por HOL llamada RECN-IQ. RECN-IQ está diseñada para conmutadores con memorias sólo a la entrada y es una técnica altamente eficiente / Mora Porta, G. (2009). High-performance architectures for high-radix switches [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/4335 / Palancia

Molluscs as well as all other invertebrates rely on innate immune response only. Their internal defense system is capable of destroying most pathogens. However, there are some exceptions, e.g. some snails serve as intermediate hosts for some trematodes. Trematodes are able to develop inside these snails due to intervention in the snail internal defense system. The submitted thesis describes hemocyte activities of two lymnaeid snails, Lymnaea stagnalis a Radix lagotis, and the influence of Trichobilharzia regenti infection on R. lagotis hemocytes. Hemocytes of both species exposed to various chemicals produced different amounts of H2O2 and NO. The response varied between both lymnaeid species. The amount of circulating hemocytes was elevated in R. lagotis snails due to T. regenti infection. However, the infenction attenuated hemocyte activities monitored by us. Hemocyte basal NO production was decreased as well as phagocytosis of bacteria, cell adherence and pseudopodia formation. Toxicity of L. stagnalis plasma against T. regenti miracidia was also described. Mechanisms used by trematodes to interact with the snail internal defense system will help us to understand why one species is suitable for the develepment of the trematode whereas another closely related species kills it. Powered by TCPDF (www.tcpdf.org)

No description available.

Field Programmable Gate Arrays (FPGAs) are increasingly being used for high-throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an order of magnitude greater sustained floating-point throughput than conventional processors. FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations, as do general purpose processors. Binary representations were chosen as the standard over three decades ago because they provide maximal numerical accuracy per bit of floating-point data. However, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point representation. From this viewpoint, higher radix floating-point representations are well suited to FPGA-based computations, especially high precision calculations which require the support of denormalized numbers. This work shows that higher radix representations lead to more efficient use of FPGA resources. For example, a hexadecimal floating-point adder provides a 30% lower Area-Time product than its binary counterpart, and a hexadecimal floating-point multiplier has a 13% lower Area-Time product than its binary counterpart. This savings occurs while still delivering equal worst-case and better average-case numerical accuracy. This work presents a family of higher radix floating-point representations that are designed specifically to interoperate with standard IEEE floating-point, allowing the creation of floating-point datapaths which operate on standard binary floating-point data, yet use higher radix representations internally. Such datapaths provide higher performance by any measure: they are more accurate numerically, consume less FPGA resources and have shorter latencies. When taking into consideration the unique nature of FPGA-based computing systems, this work shows that binary floating-point representations are not optimal for most FPGA-based arithmetic computations. Higher radix representations can therefore be a useful tool for building efficient custom floating-point datapaths on FPGAs.

Cette thèse traite le problème d'intégration hardware optimale de contrôleurs linéaires à taille de mot finie, dédiés aux applications MEMS. Le plus grand défi est d'assurer des performances de contrôle satisfaisantes avec un minimum de ressources logiques. Afin d'y parvenir, deux optimisations distinctes mais complémentaires peuvent être entreprises: en théorie de contrôle et en arithmétique binaire. Seule cette dernière est considérée dans ce travail.Comme cette arithmétique cible des applications MEMS, elle doit faire preuve de vitesse afin de prendre en charge la dynamique rapide des MEMS, à faible consommation de puissance pour un contrôle intégré, hautement re-configurabe pour un ajustement facile des performances de contrôle, et facilement prédictible pour fournir une idée précise sur les ressources logiques nécessaires avant l'implémentation même.L'exploration d'un certain nombre d'arithmétiques binaires a montré que l'arithmétique radix-2r est celle qui répond au mieux aux exigences précitées. Elle a été pleinement exploitée afin de concevoir des circuits de multiplication efficaces, qui sont au fait, le véritable moteur des systèmes linéaires.L'arithmétique radix-2r a été appliquée à l'intégration hardware de deux structures linéaires à taille de mot finie: un contrôleur PID variant dans le temps et à un contrôleur LQG invariant dans le temps,avec un filtre de Kalman. Le contrôleur PID a montré une nette supériorité sur ses homologues existants. Quant au contrôleur LQG, une réduction très importante des ressources logiques a été obtenue par rapport à sa forme initiale non optimisée / This thesis addresses the problem of optimal hardware-realization of finite-word-length(FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensuresatisfactory control performances with a minimal hardware. To come up, two distinct butcomplementary optimizations can be undertaken: in control theory and in binary arithmetic. Only thelatter is involved in this work.Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope withthe rapid dynamic of MEMS; power-efficient for an embedded control; highly scalable for an easyadjustment of the control performances; and easily predictable to provide a precise idea on therequired logic resources before the implementation.The exploration of a number of binary arithmetics showed that radix-2r is the best candidate that fitsthe aforementioned requirements. It has been fully exploited to designing efficient multiplier cores,which are the real engine of the linear systems.The radix-2r arithmetic was applied to the hardware integration of two FWL structures: a linear timevariant PID controller and a linear time invariant LQG controller with a Kalman filter. Both controllersshowed a clear superiority over their existing counterparts, or in comparison to their initial forms.

The multiple constant multiplication (MCM) operation is a fundamental operation in digital signal processing (DSP) and digital image processing (DIP). Examples of the MCM are in finite impulse response (FIR) and infinite impulse response (IIR) filters, matrix multiplication, and transforms. The aim of this work is minimizing the complexity of the MCM operation using common subexpression elimination (CSE) technique and redundant number representations. The CSE technique searches and eliminates common digit patterns (subexpressions) among MCM coefficients. More common subexpressions can be found by representing the MCM coefficients using redundant number representations. A CSE algorithm is proposed that works on a type of redundant numbers called the zero-dominant set (ZDS). The ZDS is an extension over the representations of minimum number of non-zero digits called minimum Hamming weight (MHW). Using the ZDS improves CSE algorithms' performance as compared with using the MHW representations. The disadvantage of using the ZDS is it increases the possibility of overlapping patterns (digit collisions). In this case, one or more digits are shared between a number of patterns. Eliminating a pattern results in losing other patterns because of eliminating the common digits. A pattern preservation algorithm (PPA) is developed to resolve the overlapping patterns in the representations. A tree and graph encoders are proposed to generate a larger space of number representations. The algorithms generate redundant representations of a value for a given digit set, radix, and wordlength. The tree encoder is modified to search for common subexpressions simultaneously with generating of the representation tree. A complexity measure is proposed to compare between the subexpressions at each node. The algorithm terminates generating the rest of the representation tree when it finds subexpressions with maximum sharing. This reduces the search space while minimizes the hardware complexity. A combinatoric model of the MCM problem is proposed in this work. The model is obtained by enumerating all the possible solutions of the MCM that resemble a graph called the demand graph. Arc routing on this graph gives the solutions of the MCM problem. A similar arc routing is found in the capacitated arc routing such as the winter salting problem. Ant colony optimization (ACO) meta-heuristics is proposed to traverse the demand graph. The ACO is simulated on a PC using Python programming language. This is to verify the model correctness and the work of the ACO. A parallel simulation of the ACO is carried out on a multi-core super computer using C++ boost graph library.

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).

Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS). / This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).