Many embedded systems lack a memory management unit (MMU) and thus often also lack protection of memory. This causes these systems to be less robust since the operating system (OS), processes, and threads are no longer isolated from each other. This is also a potential security issue and with the number of embedded systems rapidly increasing as a result of the rise of Internet of things (IoT), vulnerabilities like this could become a major problem. However, with a recent update to the RISC-V processor architecture, a possibility to isolate regions of memory without an MMU was introduced. This study aims to identify problems and possibilities of implementing such memory protection with RISC-V. Based on a study of literature and documentation on memory protection and the RISC-V architecture, a prototype was designed and implemented to determine potential problems and evaluate performance in terms of execution time and memory cost. The developed prototype showed aworking implementation of memory protection for the memory regions with RISC-V. The evaluation of the prototype demonstrated an increase in context switch execution time and memory usage. The results indicate that the implemented memory protection comes with an increased cost in performance with a constant factor and a small memory overhead. Therefore, it is recommended that implementations that wish to implement memory protection with RISC-V on smaller embedded systems where time and memory may be crucial takes the overhead in consideration. Further research and testing is needed to identify optimizations that could improve the performance as well as discover security flaws. / Många inbyggda system saknar en enhet för minneshantering (s.k. MMU) och saknar därför oftast minnesskydd. Detta leder till att dessa system blir mindre robusta eftersom operativsystemet, processer och trådar inte längre är isolerade från varandra. Detta är också en säkerhetsbrist och med antalet inbyggda system som snabbt ökar på grund av tillväxten av Internet of things (IoT), så kan sårbarheter som denna bli ett stort problem. Med en nyligen introducerad uppdatering av RISC-Vprocessor arkitekturen, så introducerades en möjlighet till att isolera minne utan hjälp av en MMU. Denna studie syftar till att identifiera problem och möjligheter av att implementera sådant minneskydd med RISC-V. Baserat på en studie av litteratur och dokumentation om minnesskydd och RISC-V arkitekturen designades och implementerades en prototyp för att hjälpa till att fastställa problem och möjligheter samt göra en utvärdering med avseende på prestanda- och minneskostnader. Den utvecklade prototypen visade en fungerande implementering av minneskydd för minnesregioner med RISC-V. Utvärderingen av prototypen visade en ökad exekveringstid för kontextbyten och ökad minnesanvändning. Resultaten indikerar att det implementerade minneskyddet kommer med en ökad kostnad i prestanda med en konstant faktor och en liten omkostnad i minne. Därför rekommenderas att implementeringar som vill implementera minneskydd med RISC-V på mindre inbyggda system där tid och minne kan vara avgörande tar hänsyn till omkostnaderna. Ytterligare studier och tester behövs för att identifiera optimeringar som kan förbättra prestandan och upptäcka säkerhetsbrister.

Avec les avancées récentes en microélectronique, en traitement numérique et en technologie de communication, les noeuds de réseau de capteurs sans fil (noeud RCSF) deviennent de moins en moins encombrants et coûteux. De ce fait la technologie de RCSF est utilisée dans de larges domaines d’application. Comme les noeuds RCSF sont limités en taille et en coût, ils sont en général équipés d’un petit microcontrôleur de faible puissance de calcul et de mémoire etc. De plus ils sont alimentés par une batterie donc son énergie disponible est limitée. A cause de ces contraintes, la plateforme logicielle d’un RCSF doit consommer peu de mémoire, d’énergie, et doit être efficace en calcul. Toutes ces contraintes rendent les développements de logiciels dédiés au RCSF très compliqués. Aujourd’hui le développement d’un système d’exploitation dédié à la technologie RCSF est un sujet important. En effet avec un système d’exploitation efficient, les ressources matérielles d’une plateforme RCSF peuvent être utilisées efficacement. De plus, un ensemble de services système disponibles permet de simplifier le développement d’une application. Actuellement beaucoup de travaux de recherche ont été menés pour développer des systèmes d’exploitation pour le RCSF tels que TinyOS, Contiki, SOS, openWSN, mantisOS et simpleRTJ. Cependant plusieurs défis restent à relever dans le domaine de système d’exploitation pour le RCSF. Le premier des défis est le développement d’un système d’exploitation temps réel à faible empreinte mémoire dédié au RCSF. Le second défi est de développer un mécanisme permettant d’utiliser efficacement la mémoire et l’énergie disponible d’un RCSF. De plus, comment fournir un développement d’application pour le RCSF reste une question ouverte. Dans cette thèse, un nouveau système d’exploitation hybride, temps réel à énergie efficiente et à faible empreinte mémoire nommé MIROS dédié au RCSF a été développé. Dans MIROS, un ordonnanceur hybride a été adopté ; les deux ordonnanceurs évènementiel et multithread ont été implémentés. Avec cet ordonnanceur hybride, le nombre de threads de MIROS peut être diminué d’une façon importante. En conséquence, les avantages d’un système d’exploitation évènementiel qui consomme peu de ressource mémoire et la performance temps réel d’un système d’exploitation multithread ont été obtenues. De plus, l’allocation dynamique de la mémoire a été aussi réalisée dans MIROS. La technique d’allocation mémoire de MIROS permet l’augmentation de la zone mémoire allouée et le réassemblage des fragments de mémoire. De ce fait, l’allocation de mémoire de MIROS devient plus flexible et la ressource mémoire d’un noeud RCSF peut être utilisée efficacement. Comme l’énergie d’un noeud RCSF est une ressource à forte contrainte, le mécanisme de conservation d’énergie a été implanté dans MIROS. Contrairement aux autres systèmes d’exploitation pour RCSF où la conservation d’énergie a été prise en compte seulement en logiciel, dans MIROS la conservation d’énergie a été prise en compte à la fois en logiciel et en matériel. Enfin, pour fournir un environnement de développement convivial aux utilisateurs, un nouveau intergiciel nommé EMIDE a été développé et intégré dans MIROS. EMIDE permet le découplage d’une application de système. Donc le programme d’application est plus simple et la reprogrammation à distance est plus performante, car seulement les codes de l’application seront reprogrammés. Les évaluations de performance de MIROS montrent que MIROS est un système temps réel à faible empreinte mémoire et efficace pour son exécution. De ce fait, MIROS peut être utilisé dans plusieurs plateformes telles que BTnode, IMote, SenseNode, TelosB et T-Mote Sky. Enfin, MIROS peut être utilisé pour les plateformes RCSF à fortes contraintes de ressources. / With the recent advances in microelectronic, computing and communication technologies, wireless sensor network (WSN) nodes have become physically smaller and more inexpensive. As a result, WSN technology has become increasingly popular in widespread application domains. Since WSN nodes are minimized in physical size and cost, they are mostly restricted to platform resources such as processor computation ability, memory resources and energy supply. The constrained platform resources and diverse application requirements make software development on the WSN platform complicated. On the one hand, the software running on the WSN platform should be small in the memory footprint, low in energy consumption and high in execution efficiency. On the other hand, the diverse application development requirements, such as the real-time guarantee and the high reprogramming performance, should be met by the WSN software. The operating system (OS) technology is significant for the WSN proliferation. An outstanding WSN OS can not only utilize the constrained WSN platform resources efficiently, but also serve the WSN applications soundly. Currently, a set of WSN OSes have been developed, such as the TinyOS, the Contiki, the SOS, the openWSN and the mantisOS. However, many OS development challenges still exist, such as the development of a WSN OS which is high in real-time performance yet low in memory footprint; the improvement of the utilization efficiency to the memory and energy resources on the WSN platforms, and the providing of a user-friendly application development environment to the WSN users. In this thesis, a new hybrid, real-time, energy-efficient, memory-efficient, fault-tolerant and user-friendly WSN OS MIROS is developed. MIROS uses the hybrid scheduling to combine the advantages of the event-driven system's low memory consumption and the multithreaded system's high real-time performance. By so doing, the real-time scheduling can be achieved on the severely resource-constrained WSN platforms. In addition to the hybrid scheduling, the dynamic memory allocators are also realized in MIROS. Differing from the other dynamic allocation approaches, the memory heap in MIROS can be extended and the memory fragments in the MIROS can be defragmented. As a result, MIROS allocators become flexible and the memory resources can be utilized more efficiently. Besides the above mechanisms, the energy conservation mechanism is also implemented in MIROS. Different from most other WSN OSes in which the energy resource is conserved only from the software aspect, the energy conservation in MIROS is achieved from both the software aspect and the multi-core hardware aspect. With this conservation mechanism, the energy cost reduced significantly, and the lifetime of the WSN nodes prolonged. Furthermore, MIROS implements the new middleware software EMIDE in order to provide a user-friendly application development environment to the WSN users. With EMIDE, the WSN application space can be decoupled from the low-level system space. Consequently, the application programming can be simplified as the users only need to focus on the application space. Moreover, the application reprogramming performance can be improved as only the application image other than the monolithic image needs to be updated during the reprogramming process. The performance evaluation works to the MIROS prove that MIROS is a real-time OS which has small memory footprint, low energy cost and high execution efficiency. Thus, it is suitable to be used on many WSN platforms including the BTnode, IMote, SenseNode, TelosB, T-Mote Sky, etc. The performance evaluation to EMIDE proves that EMIDE has less memory cost and low energy consumption. Moreover, it supports small-size application code. Therefore, it can be used on the high resource-constrained WSN platforms to provide a user-friendly development environment to the WSN users.

This thesis is about techniques for proving the functional correctness of Abstract Data Type (ADT) implementations. We provide a framework for proving the functional correctness of imperative language implementations of ADTs, using a theory of refinement. We develop a theory of refinement to reason about both declarative and imperative language implementations of ADTs. Our theory facilitates compositional reasoning about complex implementations that may use several layers of sub-ADTs. Based on our theory of refinement, we propose a methodology for proving the functional correctness of an existing imperative language implementation of an ADT. We propose a mechanizable translation from an abstract model in the Z language to an abstract implementation in VCC’s ghost language. Then we present a technique to carry out the refinement checks completely within the VCC tool. We apply our proposed methodology to prove the functional correctness of the scheduling-related functionality of FreeRTOS, a popular open-source real-time operating system. We focused on the scheduler-related functionality, found major deviations from the intended behavior, and did a machine-checked proof of the correctness of the fixed code. We also present an efficient way to phrase the refinement conditions in VCC, which considerably improves VCC’s performance. We evaluated this technique on a simplified version of FreeRTOS which we constructed for this verification exercise. Using our efficient approach, VCC always terminates and leads to a reduction of over 90% in the total time taken by a naive check, when evaluated on this case-study.

La conception des systèmes de contrôle embarqués devient de plus en plus complexe en raison des algorithmes utilisés, de l'augmentation des besoins industriels et de la nature des domaines d'applications. Une façon de gérer cette complexité est de concevoir les contrôleurs correspondant en se basant sur des plateformes numériques puissantes et ouvertes. Plus précisément, cette thèse s'intéresse à l'utilisation des plateformes FPGA System-on-Chip (SoC) pour la mise en œuvre des algorithmes d'entraînement électrique pour des applications avioniques. Ces dernières sont caractérisées par des difficultés techniques telles que leur environnement de travail (pression, température élevée) et les exigences de performance (le haut degré d'intégration, la flexibilité). Durant cette thèse, l'auteur a contribué à concevoir et à tester un contrôleur numérique pour un variateur de vitesse synchrone qui doit fonctionner à 200 °C de température ambiante. Il s'agit d'une commande par flux orienté (FOC) pour une Machine Synchrone à Aimants Permanents (MSAP) associée à un capteur de type résolveur. Une méthode de conception et de validation a été proposée et testée en utilisant une carte FPGA ProAsicPlus de la société Actel/Microsemi. L'impact de la température sur la fréquence de fonctionnement a également été analysé. Un état de l'art des technologies basées sur les SoC sur FPGA a été également présenté. Une description détaillée des plateformes numériques récentes et les contraintes en lien avec les applications embarquées a été également fourni. Ainsi, l'intérêt d'une approche basée sur SoC pour des applications d'entrainements électriques a été démontré. D'un autre coté et pour profiter pleinement des avantages offertes par les SoC, une méthodologie de Co-conception matériel-logiciel (hardware-software (HW-SW)) pour le contrôle d'entraînement électrique a été proposée. Cette méthode couvre l'ensemble des étapes de développement de l'application de contrôle à partir des spécifications jusqu'à la validation expérimentale. Une des principales étapes de cette méthode est le partitionnement HW-SW. Le but est de trouver une combinaison optimale entre les modules à mettre en œuvre dans la partie logiciel et celles qui doivent être mis en œuvre dans la partie matériel. Ce problème d'optimisation multi-objectif a été réalisé en utilisant l'algorithme de génétique, Non-Dominated Sorting Genetic Algorithm (NSGA-II). Ainsi, un Front de Pareto des solutions optimales peut être déduit. L'illustration de la méthodologie proposée a été effectuée en se basant sur l'exemple du régulateur de vitesse sans capteur utilisant le filtre de Kalman étendu (EKF). Le choix de cet exemple correspond à une tendance majeure dans le domaine des contrôleurs embraqués pour entrainements électriques. Par ailleurs, la gestion de l'architecture du contrôleur embarqué basée sur une approche SoC a été effectuée en utilisant un système d'exploitation temps réel. Afin d'accélérer les services de ce système d'exploitation, une unité temps réel a été développée en VHDL et associée au système d'exploitation. Il s'agit de placer les services d'ordonnanceur et des processus de communication du système d'exploitation logiciel au matériel. Ceci a permis une accélération significative du traitement. La validation expérimentale d'un contrôleur du courant a été effectuée en utilisant un banc de test du laboratoire. Les résultats obtenus prouvent l'intérêt de l'approche proposée. / Designing embedded control systems becomes increasingly complex due to the growing of algorithm complexity, the rising of industrials requirements and the nature of application domains. One way to handle with this complexity is to design the corresponding controllers on performing powerful and open digital platforms. More specifically, this PhD deals with the use of FPGA System-on-Chip (SoC) platforms for the implementation of complex AC drive controllers for avionic applications. These latters are characterized by stringent technical issues such as environment conditions (pressure, high temperature) and high performance requirements (high integration, flexibility and efficiency). During this thesis, the author has contributed to design and to test a digital controller for a high temperature synchronous drive that must operate at 200°C ambient. It consists on the Flux Oriented Controller (FOC) for a Permanent Magnet Synchronous Machine (PMSM) associated with a Resolver sensor. A design and validation method has been proposed and tested using a FPGA ProAsicPlus board from Actel-Microsemi Company. The impact of the temperature on the operating frequency has been also analyzed. A state of the art FPGA SoC technology has been also presented. A detailed description of the recent digital platforms and constraints in link with embedded applications was investigated. Thus, the interest of a SoC-based approach for AC drives applications was also established. Additionally and to have full advantages of a SoC based approach, an appropriate HW-SW Co-design methodology for electrical AC drive has been proposed. This method covers the whole development steps of the control application from the specifications to the final experimental validation. One of the main important steps of this method is the HW-SW partitioning. The goal is to find an optimal combination between modules to be implemented in software and those to be implemented in hardware. This multi-objective optimization problem was performed with the Non-Dominated Sorting Genetic Algorithm (NSGA-II). Thus, the Pareto-Front of optimal solution can be deduced. The illustration of the proposed Co-design methodology was made based on the sensorless speed controller using the Extended Kalman Filter (EKF). The choice of this benchmark corresponds to a major trend in embedded control of AC drives. Besides, the management of SoC-based architecture of the embedded controller was allowed using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration has been achieved. The experimentation tests based on digital current controller were also carried out using a laboratory set-up. The obtained results prove the interest of the proposed approach.

A data acquisition system (DAQ) was designed based on the use of a STM32 microcontroller. Its purpose is to provide a transparent and low-cost alternative to commercially available DAQs, providing educators a means to teach students about the process through which data are collected as well as the uses of collected data. The DAQ was designed to collect data from rotating machinery spinning at a speed up to 10,000 RPM and send this data to a computer through a USB 2.0 full-speed connection. Multitasking code was written for the DAQ to allow for data to be simultaneously collected and transferred over USB. Additionally, a console application was created to control the DAQ and read data, and MATLAB code written to analyze the data. The DAQ was compared against a custom assembled National Instruments CompactDAQ system. Using a Bentley-Nevada RK 4 Rotor Kit, data was simultaneously collected using both DAQs. Analysis of this data shows the capabilities and limitations of the low cost DAQ compared to the custom CompactDAQ.

This master's thesis is focused on benchmarking of Real-Time Operating Systems uC/OS-II and uC/OS-III . It describes the basic features of these systems and metrics used for benchmarking of Real-Time Operating Systems. Selected test methods are implemented and based on them are then compared the performance of Real-Time Operating Systems uC/OS-II and uC/OS-III .

This thesis aims to develop an e-health embedded system with a real-time operating system (RTOS), which allows users to monitor their body condition, including heart rate and breath, through Bluetooth Low Energy (BLE). Meanwhile, the device is also able to provide guidance for breathing by simulating breathing according to given parameters. In practice, the system samples the heart rate every two milliseconds. To ensure reliability and validity, results are expected to be sent in realtime. However, numerous data cannot be transmitted directly without being processed. Otherwise, the system will crash, and hard faults will occur. A general idea to solve this problem is to classify messages into two categories based on the priority. One is urgent, and the other is unimportant. Two solutions are proposed, one using a unidirectional linked list, and the second using queues. Based on an ARM micro-controller, the e-health embedded system is designed and implemented successfully. The evaluation results show that the solution using a linked list is suitable for the system, while the solution using queues is unable to solve the problem. With the help of the message classification, the urgent messages can be timely transmitted with continuous data. / Avhandlingen syftar till att utveckla ett e-hälso-inbyggt system med ett realtidsoperativsystem (RTOS), som gör det möjligt för användare att övervaka sitt kroppstillstånd, inklusive hjärtfrekvens och andetag, genom Bluetooth Low Energy (BLE). Samtidigt kan enheten också ge vägledning för andning genom att simulera andning enligt givna parametrar. I praktiken samplar systemet hjärtfrekvensen varannan millisekund. För att säkerställa tillförlitlighet och giltighet bör resultaten skickas i realtid. Annars kraschar systemet och allvarliga fel uppstår. En allmän idé för att lösa detta problem är att klassificera meddelanden i två kategorier baserade på prioritering, en är brådskande och den andra är obetydlig. Två lösningar föreslås, en med hjälp av riktad länkad lista och en annan implementerad med hjälp av köer. Resultatmässigt, baserat på en ARM-mikrokontroller, är det inbyggda e-hälsosystemet framgångsrikt designat och konfigurerat. Lösningen med en länkad lista är lämplig för systemet, medan lösningen som implementeras med köer fortfarande inte kan lösa problemet. Med hjälp av meddelandeklassificeringen är de brådskande meddelandena inte ens försenade med kontinuerlig data.

With the upsurge in the demand for high-bandwidth networked real-time applications in cost-sensitive environments, a key issue is to take advantage of developments of commodity components that offer a multiple of the throughput of classical real-time solutions. It was the starting hypothesis of this dissertation that with fine grained traffic shaping as the only means of node cooperation, it should be possible to achieve lower guaranteed delays and higher bandwidth utilization than with traditional approaches, even though Switched Ethernet does not support policing in the switches as other network architectures do. This thesis presents the application of traffic shaping to Switched Ethernet and validates the hypothesis. It shows, both theoretically and practically, how commodity Switched Ethernet technology can be used for low-latency hard real-time communication, and what operating-system support is needed for an efficient implementation.

This dissertation describes the development, design, implementation and evaluation of a data acquisition system, with the main aim of using it for data collection on a laboratory pilot ball mill. An open-source prototype hardware platform was utilised in the implementation of the data acquisition function, however, with limitations. An analogue signal conditioning card has been successfully developed to interface the analogue signals to the dual domain ADC module. Model-based software development was used to design and develop the algorithms to control the DAS acquisition process, but with limited capabilities. A GUI application has been developed and used for the collection and storage of the raw data on the host system. The DAS prototype was calibrated and collected data successfully through all the channels; however, the input signal bandwidth was limited to 2Hz. / Electrical and Mining Engineering / M. Tech. (Electrical Engineering)

With the upsurge in the demand for high-bandwidth networked real-time applications in cost-sensitive environments, a key issue is to take advantage of developments of commodity components that offer a multiple of the throughput of classical real-time solutions. It was the starting hypothesis of this dissertation that with fine grained traffic shaping as the only means of node cooperation, it should be possible to achieve lower guaranteed delays and higher bandwidth utilization than with traditional approaches, even though Switched Ethernet does not support policing in the switches as other network architectures do. This thesis presents the application of traffic shaping to Switched Ethernet and validates the hypothesis. It shows, both theoretically and practically, how commodity Switched Ethernet technology can be used for low-latency hard real-time communication, and what operating-system support is needed for an efficient implementation.