This work lays out the development of a reconfigurable electronic system, which is composed of biologically relevant circuits. This system has been termed a Field-Programmable Neuron Array (FPNA) and is analogous to the more familiar Field-Programmable Gate Array (FPGA) and Field-Programmable Analog Array (FPAA). At the core of the system is an array of output somas based on previously developed bio-physically based channel models. Linking them together is a complex 2D dendrite matrix, FPAA-like floating-gate routing, and associated support circuitry. Several levels of generality give this system unprecedented re-configurability. The dendrite matrix can be arbitrarily configured so that many different topologies of dendrites can be investigated. Different soma circuits can be connected / disconnected to / from the dendrite matrix. Outputs from the somas can be arbitrarily routed to input synapses that exist at each dendrite node as well as the soma nodes. Lastly, the dynamics of each node consist of a mixture of individually tunable parts and global biases. All of this can be configured in concert to investigate neural circuits that exist in biological systems. This chip will have a significant impact on research in many fields including neuroscience, neuromorphic engineering, and robotics. This chip will allow for rapid prototyping of spinal circuits. Since the fundamental circuits of the system are chosen to be biologically relevant, outputs from the various nodes should also be relevant, thus yielding itself to use by neuroscientists. This system also provides a tool by where biological systems can be emulated in real-world electronic systems. Solutions to many problems faced by roboticists (such as bi-pedal standing / walking / running / jumping / climbing and the transitions between states) are present in biology. By providing a chip that can duplicate the same neural circuits that are responsible for these processes in the biology, the hypothesis is that researchers can begin to solve some of the same types of problems in artificial systems.

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary. This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit classes by evaluating the efficiency of different architectures for each circuit class.

In this thesis, I have studied CMOS dendrites, implemented them on a reconfigurable analog platform and modeled them using MATLAB Simulink. The dendrite model was further used to build a computational model. I implemented a Hidden Markov Model (HMM) classifier to build a simple YES/NO wordspotter. I also discussed the inter-relation between neural systems, CMOS transistors and HMM networks. The physical principles behind the operation of silicon devices and biological structures are similar. Hence silicon devices can be used to emulate biological structures like dendrites. Dendrites are a branched, conductive medium which connect a neurons synapses to its soma. Dendrites were previously believed to be like wires in neural networks. However, recent research suggests that they have computational power. We can emulate dendrites using transistors in the Field Programmable Analog Array (FPAA). Our lab has built the Reconfigurable Analog Signal Processor (RASP) family of FPAAs which was used for the experiments. I analytically compared the mathematical model of dendrites to our model in silicon. The mathematical model based on the device physics of the silicon devices was then used to simulate dendrites in Simulink. An automated tool, sim2spice was then used to convert the Simulink model into a SPICE netlist, such that it can be implemented on a FPAA. This is an easier tool to use for DSP and Neuromorphic engineers who's primary areas of expertise isn't circuit design.

Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.