Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 2010

This thesis is a study of tunability of edge-coupled filters. Microstrip edge-coupled bandpass filters are planar structures and have advantages such as easy design procedures and simple integration into circuits. Three tuning techniques were implemented. The first technique involved the loading of one open end of each coupled into tunable capacitors. The second technique used a tunable resonator in series with the edge-coupled blocks. The final design made use of tunable feedback sections. A detailed mathematical analysis of each design was performed. MATLAB code based on the analyses was written. The MATLAB simulations were compared to Agilent Advanced Design System (ADS) simulations in order to and the minimum design parameters required to arrive at an approximate solution. ADS simulations were used to accurately determine the final design. The tunable filters with a series capacitor and feedback were fabricated on RO4003C boards from Roger's Corporation, having a dielectric constant of 3.55. The built boards were then tested with the HP 8510c network analyzer. The measured results were compared to the ADS simulations. The filter with a tuning capacitor in series with the coupled sections had high insertion loss of -20 dB and tuning range in terms of KHz. The design involving feedback had advantages over the previous design since the insertion loss was better than -14 dB and it had a tuning range of 91 MHz. It was observed from simulations that the design had an adjustable tunability range and bandwidth as the width was varied.

The dependence of dielectric permittivity on the applied electric field, high dielectric constant and low cost makes barium strontium titanate (BST) a promising ferroelectric material for applications in tunable microwave devices. High tunability and low dielectric loss is desired for tunable microwave devices. The primary objective of this research was to optimize the tunability and dielectric loss of BST thin films at microwave frequencies with different deposition techniques. Ba0.5Sr0.5TiO3 thin films were grown on Pt/TiO2/SiO2/Si, by pulsed laser deposition (PLD) and sputtering. Parallel plate capacitor structures were designed using ADS and fabricated. The microstructural and phase analysis of the BST films were performed using X-ray diffraction (XRD) method. The diffraction patterns are attributed to cubic (perovskite) crystal system. The analysis of surface morphology was done using atomic force microscopy. Electrical properties of parallel plate capacitors were measured using LCR meter and tunability of 2.4:1 and loss tangent of 0.05 was achieved at low frequencies for laser deposited BST thin films. Tunability of 2.8:1 and loss tangent of 0.03 was achieved at low frequencies for sputtered BST thin films. The correlation of optimized structural and dielectric properties of thin films deposited by pulsed laser deposition and sputtering technique was analyzed and compared. The structural characterization of sputtered BST thin film on MgO, Alumina and LaAl2O3 was achieved for the fabrication of interdigital capacitors. Interdigital capacitor has been designed using ADS momentum.

No description available.

Lead zirconate titanate (PZT), in the form of both bulk and thin films, is used in most piezoelectric applications due to its high piezoelectric response coefficients. Strontium-doped lead zirconate titanate (PSZT) has shown improved piezoelectric response characteristics in bulk form. This work investigates the deposition and characterisation of PSZT in the form of thin films, and reports on results from the estimation of the piezoelectric response of these thin films using two new techniques. The influence of RF magnetron sputter deposition parameters on the composition and orientation of PSZT thin films has been studied. Investigation of the consequence of varying the oxygen partial pressure during deposition on thin film stoichiometry, the influence of the choice of metal-coated silicon substrates on thin film orientation, and the effect of post-deposition cooling rate have been used to identify optimal deposition conditions. The existence of a modified unit cell resulting from these deposition parameters has been verified, and the resulting lattice parameters were estimated. Extensive materials characterisation (using microscopy, diffraction, and spectroscopy) of the PSZT thin films deposited on gold and platinum coated silicon substrates is reported. The limited techniques available for quantitative estimation of d33 for piezoelectric thin films initiated an investigation into alternative possibilities, as a consequence of which two new techniques for piezoelectric coefficient estimation, under the inverse piezoelectric effect, have been developed. One technique capitalises on the measurement accuracy of the nanoindenter in following thin film displacement, while the other uses a standard atomic force microscope in contact imaging mode to estimate d33. The development, scope, and limitations of both techniques are discussed. The techniques developed have been used to estimate the piezoelectric response of PSZT thin films. Depending on the thin film deposition parameters and the analysis frequency, values of piezoelectric response higher than any measured for thin films on silicon have been estimated. PSZT thin films deposited on gold-coated silicon at low deposition temperatures resulted in d33 values up to 892 pm/V. The study of the piezoelectric response in the millihertz frequency regime resulted in colossal values (ranging in tens of thousands of pm/V) for PSZT thin films deposited at high temperatures on platinum-coated silicon. This was hypothesised to be a result of enhanced ferroelastic domain switching. This hypothesis was verified by reducing the clamping on domains by synthesising island-structured PSZT films and obtaining an increased piezoelectric response.

Mon projet de recherche s'applique en premier lieu à développer et adapter les activités sur lesquelles je travaille depuis 14 ans, à savoir la conception et la réalisation de circuits (amplificateurs et filtres) micro-ondes pour des applications embarquées sur les répéteurs satellite. Pour illustrer cette volonté, j'ai exposé deux des thèmes de recherche (filtres multimodes en bande Ka et amplificateur de puissance à ondes travelling sur substrat silicium), sachant que j'aurai pu également évoquer le fait d'appliquer la méthode des fréquences réelles au traitement des fréquences harmoniques pour les amplificateurs fortement non-linéaires de puissance.<br />Les autres axes de recherche présentés sont tous dans le domaine de la conception de circuits dits radiofréquences. La particularité de ces circuits à application téléphonie mobile ou WLAN se situe au niveau des nouvelles techniques de conception qui diffèrent de l'approche classique du concepteur analogique ; en effet, elles font souvent intervenir des caractérisations électromagnétiques afin d'extraire des modèles électriques équivalents (balun, résonateur BAW). De plus, la montée en fréquence pour certaine des applications RF, autorisant des débits plus grands et donc des bandes passantes plus large (UWB), ou encore les systèmes multi-bande et multi-mode (GSM, DCS, PCS WCDMA, bluetooth) nécessitent des circuits d'adaptation multi-bande ou large bande dont certains pourront directement s'inspirer des architectures micro-ondes existantes.<br />Mon projet de recherche consiste donc à appliquer une approche micro-onde à la conception de circuits intégrés sur silicium. Il ne s'agit évidemment pas de la substituer à l'approche analogique classique, mais au contraire à rendre les deux approches complémentaires, afin qu'elles s'en enrichissent.

<p>In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. </p><p>To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is evaluated as well. The obtained simulation results satisfy the specification for Wi-Fi standard. </p><p>Since the RF front-end is designed for testability, the fault simulation is incorporated as well. So the performance of the front end is also evaluated for so called “spot defects”, typical of CMOS technology. They are modeled using resistive shorts or opens in the circuit.</p>

<p>To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power.Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components.In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly non-uniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed.</p>

<p>The objective of this thesis work was to implement all the hardware and software necessary to simulate the functionality of a Vector Network Analyzer (VNA). With equipment that is already available, and is common in a measurement station, the most common functions of a VNA were implemented, using an Vector Signal Generator, that provide the signal for testing, and a Vector Signal Analyzer, to make all the amplitude and phase measurements. With these instruments and the appropriate software that control them, the basic functionality of a Vector Network Analyzer can be achieved with a reasonable accuracy. With this system, we can reduce costs, avoiding the need of a real VNA and take advantage off instruments that are already available in a laboratory. A Complete measurement system of all four scattering parameters is proposed at the end of the report for future implementation. With this implementation all the different S-parameter measurements were made with an acceptable accuracy that can be comparable to a commercial VNA.</p>

Silicon Carbide (SiC) is a wide band-gap semiconductor material with excel-lent material properties for high frequency, high power and high temperature elec-tronics. In this work different SiC field-effect transistors have been studied using theoretical methods, with the focus on both the devices and the methods used. The rapid miniaturization of commercial devices demands better physical models than the drift-diffusion and hydrodynamic models most commonly used at present. The Monte Carlo method is the most accurate physical methods available and has been used in this work to study the performance in short-channel SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power required and it is thus not well suited for device design where the layout requires to be optimized for best device performance. One approach to reduce the simulation time in the Monte Carlo method is to use a time-domain drift-diffusion model in contact and bulk regions of the device. In this work, a time-domain drift-diffusion model is implemented and verified against commercial tools and would be suitable for inclusion in the Monte-Carlo device simulator framework. Device optimization is traditionally performed by hand, changing device pa-rameters until sufficient performance is achieved. This is very time consuming work without any guarantee of achieving an optimal layout. In this work a tool is developed, which automatically changes device layout until optimal device per-formance is achieved. Device optimization requires hundreds of device simulations and thus it is essential that computationally efficient methods are used. One impor-tant physical process for RF power devices is self heating. Self heating can be fairly accurately modeled in two dimensions but this will greatly reduce the computa-tional speed. For realistic influence self heating must be studied in three dimensions and a method is developed using a combination of 2D electrical and 3D thermal simulations. The accuracy is much improved by using the proposed method in comparison to a 2D coupled electro/thermal simulation and at the same time offers greater efficiency. Linearity is another very important issue for RF power devices for telecommunication applications. A method to predict the linearity is imple-mented using nonlinear circuit simulation of the active device and neighboring passive elements.