This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.

Les amplificateurs de puissance, éléments constitutifs essentiels de tout système de télécommunication, vont jouer un rôle capital dans le développement des futurs systèmes de communication. Aujourd'hui l'amélioration des amplificateurs de puissance nécessite un progrès technologique au niveau du composant lui même mais doit aussi tenir compte d'une approche plus globale. En particulier, le progrès dans les traitements numériques permet aujourd'hui de corriger en amont certaines distorsions qui seront générées en aval de la chaîne de communication. La pré-distorsion numérique est une technique de correction des amplificateurs de puissance qui connaît un intérêt grandissant de par son intégration complètement numérique et par les gains en linéarité et en consommation. Cette technique nécessite une voie de retour dont un élément critique est le convertisseur analogique-numérique. Ce composant doit répondre à des contraintes de résolution, de bande passante et de linéarité élevées. Dans cette thèse, nous proposons une nouvelle architecture de convertisseur analogique-numérique à base de modulateurs Sigma-Delta passe-bande. Cette architecture tire partie du fonctionnement passe bande des modulateurs que nous faisons travailler en parallèle, chacun centré sur différentes fréquences, mais aussi d'un agencement en cascade particulier pour éliminer le signal utile, qui est de forte puissance, dans le but de diminuer les contraintes de dynamique.La conception haut niveau et les simulations ont été menées pour des systèmes à temps discret et aussi à temps continu et a nécessité le développement d'outils adaptés de simulation se basant sur la boîte à outils Delta Sigma Toolbox de Richard Schreier / Power amplifiers, which are essential elements of any communication system, will play a crucial role in the development of future communication systems. Today improving power amplifiers requires technological advances at the circuit device level, but one also must consider a more global approach. In particular, advances in digital processing can now correct in the early stage of the communication chain some distortions that are generated downstream in the chain. Digital pre-distortion is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and of its gains in linearity and energy consumption. This technique requires a feedback path where the analog-to-digital converter is a critical element. This component must satisfy the constraints of high resolution , wide bandwidth, and high linearity. In this thesis, we propose a new architecture of analog-to-digital converter based on bandpass Delta-Sigma modulators. This architecture takes advantage of operating bandpass modulators that are designed to work in parallel, each focusing on different frequencies, but also of a particular cascading arrangement to eliminate the useful signal, which has a high power, in order to reduce dynamics constraints. High-level design and simulations were carried out for discrete time and continuous time systems and also required the development of appropriate simulation tools.

Cette thèse porte sur la conception et la réalisation de convertisseurs analogique/numérique (ADC) haute résolution dans le domaine de l’imagerie spatiale en technologie 0.18 μm.Un imageur CMOS est un système destiné à acquérir des informations lumineuses et les convertir en données numériques afin que cellesci soient traitées. Ce système est composé d’une matrice de pixels, d’ADC, de registres et de blocs de signaux de commande afin de rendre toutes ces données disponibles. Avec la taille grandissante de la matrice de pixels et la cadence d’image par seconde croissante, l’ADC doit réaliser de plus en plus de conversions en moins de temps et est donc devenu l’un des « bottleneck » les plus importants dans les systèmes d’imagerie. Une solution adaptée a donc été le développement d’ADC colonne situé en bout de colonnes de pixels afin de réaliser des conversions en parallèles et c’est ce sujet qui va m’intéresser.Dans une première partie, n’ayant pas de contraintes sur l’architecture d’ADC à utiliser, une étude de l’état de l’art des ADC pour l’imagerie est réalisée ainsi que les spécifications visées pour notre application. Une architecture sigma-delta incrémental à deux étapes semble la plus prometteuse et va être développée. Ensuite, une étude théorique de l’ADC choisi, et plus particulièrement du modulateur sigma-delta à utiliser est effectuée, afin notamment de déterminer l’ordre de ce modulateur, mais également le nombre de cycles de cette conversions. Une fois les paramètres de modélisation définis, un schéma transistor est réalisé au niveau transistor, avec une particularité au niveau de l’amplificateur utilisé. En effet, afin de gagner en surface qui est l’un des points importants dans les systèmes d’imagerie, un inverseur est utilisé. Une étude de cette inverseur, afin de choisir le plus adapté à notre besoin est effectuée avec des simulations montecarlo et aux « corners ». Pour finir, un routage global de l’ADC est réalisé afin de pouvoir comparer ces performances à l’état de l’art. / This thesis deals with the conception and design of high resolution analog-to-digital converters (ADC) for CMOS image sensor (CIS) applications with the 0.18 μm technology. A CIS is a system able to convert light to digital data to be processed. This system includes a pixel array, ADCs, registers and a set of clocks to acquire and transport the data. At the beginning, a single ADC was used for the whole matrix of pixels, converting the pixel value in a sequential way. With the growing size of the pixel array and the increasing frame rate, the ADC became one of the bottleneck of these system. A solution was found to use column ADC, located at the bottom of each column in order to parallelize the conversions. These column ADC are going to be my point of interest in this thesis.First of all, a state of the art of the ADC for CIS is realized in order to determine the best architecture to use. A two-step incremental sigma-delta is chosen and investigated. A theoretical analysis is done, especially on the modulator in order to determine the order of this modulator and the oversampling ratio of the conversion. Then a schematic is realized, with a special feature on the amplifier. Indeed, an inverter is used as amplifier in order to reduce the size of the ADC. A montecarlo and corner studies are then realized on the ADC, a layout is proposed and the ADC is compared to the state of the art of the ADC for CIS.

No description available.

<p>In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.</p>

In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.

<p>Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.</p>

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Universidade do Porto. Faculdade de Engenharia. 2011

Le convertisseur analogique-numérique fondé sur le principe de modulation SD est capable de fournir une très haute résolution. Bien qu'il nécessite un suréchantillonnage, il est peu sensible aux imperfections des composants. Le modulateur SD classique est donc très populaire pour les applications de bande étroite demandant une très haute résolution. Dans cette thèse, nous nous sommes intéressés à l'extension des applications du modulateur SD vers une bande passante plus large. Nous avons tout d'abord étudié l'architecture parallèle basant sur la modulation SD et proposé une nouvelle architecture basant sur la modulation SD passe-haut et l'entrelacement temporel permettant de réduire de façon significative le problème caractéristique du parallélisme, à savoir la disparité entre les canaux. Nous avons ensuite étudié le modulateur SD passe-haut et proposé une implémentation en technique des capacités commutées. Ce nouveau modulateur, contrairement au modulateur classique, est complètement immune au bruit de basse fréquence et peut être utilisé non seulement dans une architecture parallèle, mais aussi de façon autonome. Nous avons aussi modélisé la plupart de non-idéalités du modulateur en VHDL-AMS pour finalement arriver à une méthodologie de conception descendante qui permet de dériver les spécifications de tous les blocs du circuit à partir de performance visée pour le système complet. L'implémentation d'un modulateur SD passe-haut d'ordre 2 et un convertisseur SD passe-haut en combinant avec l'entrelacement temporel a été réalisée en technologie CMOS 0,35 mm. Enfin, notre travail nous a permis de démontrer non seulement l'avantage du modulateur SD passe-haut, mais aussi un perspective prometteur du modulateur SD parallèle pour les applications de très large bande.

<p>The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity. </p><p>High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.</p>