As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.

The corrosion resistance of two commercially available SiC filter materials coated with Mg-doped Al₂ TiO₅ and (Ca _0.6.6' Mg_0.52) Zr₄P₆O₂₄ (CMZP) was investigated in high-temperature high pressure (HTHP) alkali-steam environments. Coated specimen properties, including cold and hot compressive strengths, bulk density, apparent porosity, permeability, and weight change, detected after exposure to 92% air-S% steam 10 ppm Na at 8OO°C and 1.8 MPs for 500 h were compared with those of uncoated specimens. Procedures for applying homogeneous coatings of Mg-doped Al₂ TiO₅ and CMZP to porous SiC filters were established and coating of the materials was successfully accomplished. Efforts to stabilize the Al₂ TiO₅ coating composition at elevated temperature were successful. Coatings show promise for providing improved corrosion resistance of the materials in pressurized fluidized bed combustion (PFBC) environments as evidenced by higher compressive strengths exhibited by coated SiC specimens than by uncoated SiC specimens following HTHP alkali-steam exposure. / Master of Science

Silicon carbide and nanostructured ferritic alloy (SiC-NFA) composites have the potential to maintain the outstanding high temperature corrosion and irradiation resistance and enhance the mechanical integrity for nuclear cladding. However, the formation of detrimental silicide phases due to reaction between SiC and NFA remains a major challenge. By introducing a carbon interfacial barrier on NFA (C@NFA), SiC-C@NFA composites are investigated to reduce the reaction between SiC and NFA. In a similar way, the effect of chromium carbide (Cr3C2) interfacial barrier on SiC (Cr3C2@SiC) is also presented for Cr3C2@SiC-NFA composites. Both the coatings were successful in suppressing silicide formation. However, despite the presence of coatings, SiC was fully consumed during spark plasma sintering process. TEM and EBSD investigations revealed that spark plasma sintered SiC-C@NFA and Cr3C2@SiC-NFA formed varying amounts of different carbides such as (Fe,Cr)7C3, (Ti,W)C and graphite phases in their microstructure. Detailed microstructural examinations after long term thermal treatment at 1000oC on the microstructure of Cr3C2@SiC-NFA showed precipitation of new (Fe,Cr)7C3, (Ti,W)C carbides and also the growth of existing and new carbides. The results were successfully explained using ThermoCalc precipitation and coarsening simulations respectively. The oxidation resistance of 5, 15 and 25 vol% SiC@NFA and Cr3C2@SiC-NFA composites at 500-1000oC temperature under air+45%water vapor containing atmosphere is investigated. Oxidation temperature effects on surface morphologies, scale characteristics, and cross-sectional microstructures were investigated and analyzed using XRD and SEM. SiC-C@NFA showed reduced weight gain but also showed considerable internal oxidation. Cr3C2@SiC-NFA composites showed a reduction in weight gain with the increasing volume fraction of Cr3C2@SiC (5, 15 and 25) without any indication of internal oxidation in the microstructure. 25 vol% SiC-C@NFA and 25 vol% Cr3C2@SiC-NFA showed over 90% and 97% increase in oxidation resistance (in terms of weight gain) as compared to NFA. The results were explained using the fundamental understanding of the oxidation process and ThermoCalc/DICTRA simulations. Finally, the irradiation performance of SiC-C@NFA and Cr3C2@SiC-NFA composites was assessed in comparison with NFA using state-of-the-art TEM equipped with in-situ ion irradiation capability. Kr++ ions with 1 MeV energy was used for irradiation experiments. The effect of ion irradiation was recorded after particular dose levels (0-10 dpa) at 300oC and 450oC temperatures. NFA sample showed heavy dislocation damage at both 300oC and 450oC increasing gradually with dose levels (0-10 dpa). Cr3C2@SiC-NFA showed similar behavior as NFA at 300oC. However, at 450oC, Cr3C2@SiC-NFA showed remarkably low dislocation loop density and loop size as compared to NFA. At 300oC, microstructures of NFA and Cr3C2@SiC-NFA show predominantly 1/2<111> type dislocation loops. At 450oC, NFA showed predominantly <100> type loops, however, Cr3C2@SiC-NFA composite was still predominant in ½<111> loops. The possible reasons for this interesting behavior were discussed based on the large surface sink effects and enhanced interstitial-vacancy recombination at higher temperatures. The molecular dynamics simulations did not show considerable difference in formation energies of ½<111> and <100> loops for NFA and Cr3C2@SiC-NFA composites. The additional Si element in the SiC-NFA sample could have been an important factor in determining the dominant loop types. SiC-C@NFA composites showed heavy dislocation damage during irradiation at 300oC. At 450oC, SiC-C@NFA showed high dislocation damage in thicker regions. Thinner regions near the edge of TEM samples were largely free from dislocation loops. The precipitation and growth of new (Ti,W)C carbides were observed at 450oC with increasing irradiation dose. (Fe,Cr)7C3 precipitates were largely free from any dislocation damage. Some Kr bubbles were observed inside (Fe,Cr)7C3 precipitates and at the interface between α-ferrite matrix and carbides ((Fe,Cr)7C3, (Ti,W)C). The results were discussed using the fundamental understanding of irradiation and ThermoCalc simulations. / Doctor of Philosophy / With the United Nations describing climate change as 'the most systematic threat to humankind', there is a serious need to control the world's carbon emissions. The ever increasing global energy needs can be fulfilled by the development of clean energy technologies. Nuclear power is an attractive option as it can produce low cost electricity on a large scale with greenhouse gas emissions per kilowatt-hour equivalent to wind, hydropower and solar. The problem with nuclear power is its vulnerability to potentially disastrous accidents. Traditionally, fuel claddings, rods which encase nuclear fuel (e.g. UO2), are made using zirconium based alloys. Under 'loss of coolant accident (LOCA) scenarios' zirconium reacts with high temperature steam to produce large amounts of hydrogen which can explode. The risks associated with accidents can be greatly reduced by the development of new accident tolerant materials. Nanostructured ferritic alloys (NFA) and silicon carbide (SiC) are long considered are leading candidates for replacing zirconium alloys for fuel cladding applications. In this dissertation, a novel composite of SiC and NFA was fabricated using spark plasma sintering (SPS) technology. Chromium carbide (Cr3C2) and carbon (C) coatings were employed on SiC and NFA powder particles respectively to act as reaction barrier between SiC and NFA. Microstructural evolution after spark plasma sintering was studied using advanced characterization tools such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) techniques. The results revealed that the Cr3C2 and C coatings successfully suppressed the formation of detrimental reaction products such as iron silicide. However, some reaction products such as (Fe,Cr)7C3 and (Ti,W)C carbides and graphite retained in the microstructure. This novel composite material was subjected to high temperature oxidation under a water vapor environment to study its performance under the simulated reactor environment. The degradation of the material due to high temperature irradiation was studied using state-of-the-art TEM equipped with in-situ ion irradiation capabilities. The results revealed excellent oxidation and irradiation resistance in SiC-NFA composites as compared to NFA. The results were discussed based on fundamental theories and thermodynamic simulations using ThermoCalc software. The findings of this dissertation imply a great potential for SiC-NFA based composites for future reactor material designs.

As the boundaries of Moore's Law rapidly approach, research is increasingly turning to exotic materials and metamaterials to advance the capabilities of electronic and micromechanical systems. This thesis presents systems, models, and simulation techniques for novel microfabrication in the realms of silicon carbide (SiC) and metal mesh filters. Through the unification of femtosecond laser pulses, high numerical aperture (NA) objective lenses, and system power and motion control, a system capable of achieving arbitrary 3D features without line-of-sight with aspect ratios up to 109:1 in SiC is developed. Additionally, a model of a direct-write femtosecond-laser-ablation fabricated metal mesh filter (MMF) is simulated in ANSYS High Frequency Structure Simulator (HFSS) and validates the novel fabrication technique. Finally, a transmission-line-theory based MMF model is presented as an alternative to modelling multilayer filters in HFSS. This model produces comparable results to an HFSS simulation with dramatically reduced computational intensity.

Silicon carbide (SiC) power switching devices promise to be a major breakthrough for new generation ac three-phase power converters, offering increased junction temperature, low specific on-resistance, fast switching, and low switching loss. These characteristics are desirable for increasing power density, providing faster system dynamics, and improving power quality. At present, the normally-on SiC JFET prototypes available from SiCED are the first SiC power switches close to commercialization. The objective of this work is to characterize the switching behavior of the prototype SiC JFET devices, as well as demonstrate the feasibility of achieving high switching frequency for a 2 kVA three-phase converter. The switching characterization of the 1200 V SiC JFET prototypes is shown for a wide range of operating conditions such as switched voltage, switched current, and junction temperature. The SiC JFET is shown to be a fast-switching, low-loss device offering performance benefits compared to traditional silicon (Si) power devices of similar ratings. Utilizing the SiC JFET, a three-phase ac buck rectifier is then demonstrated with a 150 kHz switching frequency and a rated power of 2 kVA. Additionally, improvements are made to the charge control scheme for the buck rectifier allowing power factor compensation and reduction of input current transients. / Master of Science

This work investigates three-dimensional power loop layout for application to a SiC based matrix converter, providing a symmetric, low-inductance solution. The thesis presents various layout types to achieve this design target, and details the implementation of a hybrid layout to the matrix converter phase-leg. This layout is more easily achievable with a surface-mount device package, which also offers benefits such as ease in manufacturing, and a compact package. In order to implement a surface-mount device, a PCB thermal management strategy should be utilized. An evaluation of these methods is also presented in the work. The final power loop solution that implements an aluminum nitride inlay is evaluated through simulated parasitic extraction and experimental double pulse tests. The layout achieves small, symmetric loop inductances. Finally, the full power, three-phase matrix converter demonstrates the successful implementation of this power loop layout. / Master of Science / In the United States, 40% primary energy consumption comes from electricity generation, which is the fastest growing form of end-use energy. Industries such as commercial airlines are increasing their use of electric energy, while phasing out the mechanical and pneumatic aircraft components, as they offer better performance and lower cost. Thus, implementation of high efficiency, electrical system can reduce energy consumption, fuel consumption and carbon emissions [1]. As more systems rely on this electric power, the conversion from one level of power (voltage and current) to another, is critical. In the quest to develop high efficiency power converters, wide bandgap semiconductor devices are being turned to. These devices, specifically Silicon Carbide (SiC) devices, offer high temperature and high voltage operation that a traditional Silicon (Si) device cannot. Coupled with fast switching transients, these metal oxide semiconductors field effect transistors (MOSFETs), could provide higher levels of efficiency and power density. This work investigates the benefits of a three-dimensional (3D) printed circuit board (PCB) layout. With this type of layout, a critical parasitic – inductance – can be minimized. As the SiC device can operate at high switching speeds, they incur higher di/dt, and dv/dt slew rates. If trace inductance is not minimal, overshoots and ringing will occur. This can be addressed by stacking PCB traces on top of one another, the induced magnetic field can be reduced. In turn, the system inductance is lowered as well. The reduction of this parameter in the system, reduces the overshoot and ringing. This particular work applies this technique to a 15kW matrix converter. This converter poses a particular design challenge as there are a large number of devices, which can lead to longer, higher inductance PCB traces. The goal of this work is to minimize the parasitic inductance in this converter for high efficiency, high power density operation.

A finite element analysis (FEA) driven, automated numerical optimization technique is used to design electric field grading structures in a PCB-integrated bus bar for a 10 kV bondwire-less silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, careful design of field-grading structures inside the bus bar is required to mitigate the high electric field strength in the air. Using Bayesian optimization and a new weighted point-of-interest (POI) cost function, the highly non-uniform electric field is efficiently optimized without the use of field integration, or finite-difference derivatives. The proposed optimization technique is used to efficiently characterize the performance of the embedded field grading structure, providing insights into the fundamental limitations of the system. The characterization results are used to streamline the design and optimization of the bus bar and high-density module interface. The high-density interface experimentally demonstrated a partial discharge inception voltage (PDIV) of 11.6 kV rms. When compared to a state-of-the-art descent-based optimization technique, the proposed algorithm converges 3x faster and with 7x smaller error, making both the field grading structure and the design technique widely applicable to other high-density high-voltage design problems. / M.S. / Innovation trends in electrical engineering such as the electrification of consumer and commercial vehicles, renewable energy, and widespread adoption of personal electronics have spurred the development of new semiconductor materials to replace conventional silicon technology. To fully take advantage of the better efficiency and faster speeds of these new materials, innovation is required at the system-level, to reduce the size of power conversion systems, and develop converters with higher levels of integration. As the size of these systems decreases, and operating voltages rise, the design of the insulation systems that protect them becomes more critical. Historically, the design of high-density insulation system requires time-consuming design iteration, where the designer simulates a case, assesses its performance, modifies the design, and repeats, until adequate performance is achieved. The process is computationally expensive, time-consuming, and the results are not easily applied to other insulation design problems. This work proposes an automated design process that allows for the streamlined optimization of high-density insulation systems. The process is applied to a 10 kV power module and experimentally demonstrates a 38\% performance improvement over manual design techniques, while providing an 8 times reduction in design cycle time.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

This report collects selected outstanding scientific and technological results obtained within the frame of the European project "FLASiC" (Flash LAmp Supported Deposition of 3C-SiC) but also other work performed in adjacent fields. Goal of the project was the production of large-area epitaxial 3C-SiC layers grown on Si, where in an early stage of SiC deposition the SiC/Si interface is rigorously improved by energetic electromagnetic radiation from purpose-built flash lamp equipment developed at Forschungszentrum Rossendorf. Background of this work is the challenging task for areas like microelectronics, biotechnology, or biomedicine to meet the growing demands for high-quality electronic sensors to work at high temperatures and under extreme environmental conditions. First results in continuation of the project work – for example, the deposition of the topical semiconductor material zinc oxide (ZnO) on epitaxial 3C-SiC/Si layers – are reported too.