Les travaux présentés dans cette thèse portent sur la modélisation, la spécification et la vérification des modèlesdes Systèmes sur Puce (SoCs) au niveau d’abstraction transactionnel et à un niveau d’abstraction plus élevé.Les SoCs sont hétérogènes: ils comprennent des composants matériels et des processeurs pour réaliser le logicielincorporé, qui est en lien direct avec du matériel. La modélisation transactionnelle (TLM) basée sur SystemCa été très fructueuse à fournir des modèles exécutables des SoCs à un haut niveau d’abstraction, aussi appelésprototypes virtuels (VPs). Ces modèles peuvent être utilisés plus tôt dans le cycle de développement des logiciels,et la validation des matériels réels. La vérification basée sur assertions (ABV) permet de vérifier les propriétés tôtdans le cycle de conception de façon à trouver les défauts et faire gagner du temps et de l’effort nécessaires pourla correction de ces défauts. Les modèles TL peuvent être sur-contraints, c’est-à-dire qu’ils ne presentent pastous les comportements du matériel. Ainsi, ceci ne permet pas la détection de tous les défauts de la conception.Nos contributions consistent en deux parties orthogonales et complémentaires: D’une part, nous identifions lessources des sur-contraintes dans les modèles TLM, qui apparaissent à cause de l’ordre d’interaction entre lescomposants. Nous proposons une notion d’ordre mou qui permet la suppression de ces sur-contraintes. D’autrepart, nous présentons un mécanisme généralisé de stubbing qui permet la simulation précoce avec des prototypesvirtuels SystemC/TLM.Nous offrons un jeu de patrons pour capturer les propriétés d’ordre mou et définissons une transformationdirecte de ces patrons en moniteurs SystemC. Notre mécanisme généralisé du stubbing permet la simulationprécoce avec les prototypes virtuels SystemC/TLM, dans lesquels certains composants ne sont pas entièrementdéterminés sur les valeurs des données échangées, l’ordre d’interaction et/ou le timing. Ces composants nepossèdent qu’une spécification abstraite, sous forme de contraintes entre les entrées et les sorties. Nous montronsque les problèmes essentielles de la synchronisation entre les composants peuvent être capturés à l’aide de notresimulation avec les stubs. Le mécanisme est générique; nous mettons l’accent uniquement sur les concepts-clés,les principes et les règles qui rendent le mécanisme de stubbing implémentable et applicable aux études de casindustriels. N’importe quel language de spécification satisfaisant nos exigences (par ex. le langage des ordresmou) peut être utilisé pour spécifier les composants, c’est-à-dire il peut être branché au framework de stubbing.Nous fournissons une preuve de concept pour démontrer l’intérêt d’utiliser la simulation avec stubs pour ladétection anticipée et la localisation des défauts de synchronisation du modèle. / The work presented in this thesis deals with modeling, specification and testing of models of Systems-on-a-Chip (SoCs) at the transaction abstraction level and higher. SoCs are heterogeneous: they comprise bothhardware components and processors to execute embedded software, which closely interacts with hardware.SystemC-based Transaction Level Modeling (TLM) has been very successful in providing high-level executablecomponent-based models for SoCs, also called virtual prototypes (VPs). These models can be used early in thedesign flow for the development of the software and the validation of the actual hardware. For SystemC/TLMvirtual prototypes, Assertion-Based Verification (ABV) allows property checking early in the design cycle,helping to find bugs early in the model and to save time and effort that are needed for their fixing. TL modelscan be over-constrained, which means that they do not represent all the behaviors of the hardware, and thus,do not allow detection of some malfunctions of the prototype. Our contributions consist of two orthogonal andcomplementary parts: On the one hand, we identify sources of over-constraints in TL models appearing due tothe order of interactions between components, and propose a notion of loose-ordering which allows to removethese over-constraints. On the other hand, we propose a generalized stubbing mechanism which allows the veryearly simulation with SystemC/TLM virtual prototypes.We propose a set of patterns to capture loose-ordering properties, and define a direct translation of thesepatterns into SystemC monitors. Our generalized stubbing mechanism enables the early simulation with Sys-temC/TLM virtual prototypes, in which some components are not entirely determined on the values of theexchanged data, the order of the interactions and/or the timing. Those components have very abstract speci-fications only, in the form of constraints between inputs and outputs. We show that essential synchronizationproblems between components can be captured using our simulation with stubs. The mechanism is generic;we focus only on key concepts, principles and rules which make the stubbing mechanism implementable andapplicable for real, industrial case studies. Any specification language satisfying our requirements (e.g., loose-orderings) can be used to specify the components, i.e., it can be plugged in the stubbing framework. We providea proof of concept to demonstrate the interest of using the simulation with stubs for very early detection andlocalization of synchronization bugs of the design.

AIDS-related human cytomegalovirus (HCMV) retinitis remains the leading cause of blindness among untreated HIV/AIDS patients worldwide. Understanding the pathogenesis of this disease is essential for developing new, safe, and effective treatments for its prevention or management, yet much remains unknown about the virologic and immunologic mechanisms contributing to its pathology. To study such mechanisms, we use a well-established, reproducible, and clinically relevant animal model with retrovirus-induced murine acquired immunodeficiency syndrome (MAIDS) that mimics in mice the symptoms and progression of AIDS in humans. Over 8 to 12 weeks, MAIDS mice become susceptible to experimental murine cytomegalovirus (MCMV) retinitis. We have found in this model that MCMV infection significantly stimulates ocular suppressor of cytokine signaling (SOCS)1 and SOCS3, host proteins which dampen immune-related signaling by cytokines, including antiviral interferons. Herein we investigated virologic and/or immunologic mechanisms involved in this stimulation and how virally-modulated SOCS1 and/or SOCS3 proteins may contribute to MCMV infection or experimental MAIDS-related MCMV retinitis. Through pursuit of two specific aims, we tested the central hypothesis that MCMV stimulates and employs SOCS1 and/or SOCS3 to induce the onset and development of MCMV retinal disease. MCMV-related SOCS1 and SOCS3 stimulation in vivo occurred with intraocular infection, was dependent on method and stage of immune suppression and severity of ocular pathology, was associated with stimulation of SOCS-inducing cytokines, and SOCS1 and SOCS3 were differentially sensitive to antiviral treatment. In vitro studies further demonstrated that SOCS1 and SOCS3 stimulation during MCMV infection occurred with expected immediate early kinetics, required viral gene expression in cell-type-dependent and virus origin-dependent patterns of expression, and displayed differential sensitivity to antiviral treatment. These data suggest that SOCS1 and SOCS3 are stimulated by divergent virologic, immunologic, and/or pathologic mechanisms during MCMV infection, and that they contribute to the pathogenesis of retinal disease, revealing new insights into the pathophysiology of AIDS-related HCMV retinitis.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível para FPGAs (Field Programmable Gate Array), ou seja, circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SOC). Através de um injetor de falhas por emulação usando o ICAP (Internal Configuration Access Port) localizado dentro do FPGA é possível injetar falhas simples ou acumuladas do tipo SEU (Single Event Upset), definidas como perturbações que podem afetar o funcionamento correto do dispositivo através da inversão de um bit por uma partícula carregada. SEU está dentro da classificação de SEEs (Single Event Effects), efeitos transitórios em tradução livre, podem ocorrer devido a penetração de partículas de alta energia do espaço e do sol (raios cósmicos e solares) na atmosfera da Terra que colidem com átomos de nitrogênio e oxigênio resultando na produção de partículas carregadas, na grande maioria nêutrons. Dentro deste contexto além de analisar a suscetibilidade de projetos gerados por ferramenta de Síntese de Alto Nível, torna-se relevante o estudo de técnicas de redundância como TMR (Triple Modular Redundance) para detecção, correção de erros e comparação com projetos desprotegidos verificando a confiabilidade. Os resultados mostram que no modo de injeção de falhas simples os projetos com redundância TMR demonstram ser efetivos. Na injeção de falhas acumuladas o projeto com múltiplos canais apresentou melhor confiabilidade do que o projeto desprotegido e com redundância de canal simples, tolerando um maior número de falhas antes de ter seu funcionamento comprometido. / This work consists of the study and analysis of the susceptibility to effects of radiation in circuits projects generated by High Level Synthesis tool for FPGAs Field Programmable Gate Array (FPGAs), that is, system-on-chip (SOC). Through an emulation fault injector using ICAP (Internal Configuration Access Port), located inside the FPGA, it is possible to inject single or accumulated failures of the type SEU (Single Event Upset), defined as disturbances that can affect the correct functioning of the device through the inversion of a bit by a charged particle. SEU is within the classification of SEEs (Single Event Effects), can occur due to the penetration of high energy particles from space and from the sun (cosmic and solar rays) in the Earth's atmosphere that collide with atoms of nitrogen and oxygen resulting in the production of charged particles, most of them neutrons. In this context, in addition to analyzing the susceptibility of projects generated by a High Level Synthesis tool, it becomes relevant to study redundancy techniques such as TMR (Triple Modular Redundancy) for detection, correction of errors and comparison with unprotected projects verifying the reliability. The results show that in the simple fault injection mode TMR redundant projects prove to be effective. In the case of accumulated fault injection, the multichannel design presented better reliability than the unprotected design and with single channel redundancy, tolerating a greater number of failures before its operation was compromised.

L'augmentation de la complexité des systèmes hétérogènes a conduit à l'apparition d'une nouvelle méthode de conception et de validation. Cette approche qui s'appuie sur un flot de conception descendant s'inspire des méthodes utilisées dans le domaine numérique. Dans cette thèse, nous avons développé une approche permettant de qualifier le plan de vérification utilisé lors de la validation de conception et d'améliorer le test matériel des systèmes AMS&RF. L'originalité de notre approche est d'utiliser une description comportementale du système pour la qualification et la génération des stimuli de test. En effet, les méthodes de test actuelles utilisant les descriptions niveau composant ne sont pas adaptées au test de systèmes complexes. En utilisant ce concept, au cours de cette thèse la plateforme PLASMA, PLAteforme pour la qualification et la génération de stimuli pour test de Systèmes Mixtes et Analogiques, a été développée. Cette plateforme est en particulier conçue pour le test des systèmes AMS&RF. PLASMA a été validée sur un émetteur/récepteur W-CDMA intégré conçu par ST Microelectronics.

L'hormone de croissance (GH) est une hormone paradoxale. Historiquement reconnue comme responsable de la croissance post-natale, elle est actuellement considérée comme une véritable cytokine, synthétisée en de nombreux sites extra-hypophysaires et impliquée, lorsque dérégulée, dans les processus de tumorigénèse. Le travail présenté dans cette thèse a permis de caractériser et localiser par RT-PCR in situ, les cellules capables de synthétiser la GH dans le système immunitaire du fœtus et du rat adulte, puis dans les différents systèmes de prolifération cellulaire du carcinome canalaire mammaire humain montrant ainsi que la GH, par son action autocrine / paracrine est non seulement impliquée dans le développement embryonnaire mais participe à la progression tumorale. Nos travaux in vitro montrent que l'internalisation et la translocation nucléaire de la GH complexée à son récepteur sont indépendantes de l'activation de JAK2 « Janus Kinase 2 », cependant indispensable à son exportation hors du noyau. L'étude du système de régulation négative du signal induit par la GH nous a permis de mettre en évidence une surexpression de la protéine CIS « Cytokine-Inducible SH2-containing protein », dans les zones de prolifération tumorale des différents carcinomes étudiés et dans 8 lignées tumorales mammaires. La surexpression de CIS, in vitro, inhibe la voie de signalisation JAK/STAT « Signal Transducer and Activator of Transcription » et active la voie des MAPK « Mitogen Activated Protein Kinases ». Nous avons pour finir, corrélé l'activation prédominante de CIS à la synthèse de GH « autocrine » dans les cellules tumorales mammaires MCF-hGH. La localisation tant nucléaire que cytoplasmique de la GH et de toutes les molécules informatives laisse entrevoir des mécanismes de régulation encore inconnus. Les travaux futurs tenteront de répondre à la question maintenant cruciale : la GH, hormone de jouvence ou véritable oncogène ?

La protéine SOCS-1 (Suppressor Of Cytokine Signalling 1) a été historiquement caractérisée comme un régulateur négatif de la voie de signalisation JAK/STAT. Cette dernière, activée en réponse à de nombreuses cytokines, hormones et facteurs de croissance, aboutit à l'expression de nombreux gènes cibles, dont le gène codant pour la protéine SOCS-1. Dans un premier travail, nous avons étudié la régulation du gène Socs-1 après une stimulation par l'interféron-gamma. Nous avons ainsi mis en évidence l'implication des facteurs de transcription IRF-1 et Sp2 dans la régulation transcriptionnelle du gène Socs-1. Dans de nombreuses tumeurs humaines, l'expression du gène Socs-1 est inhibée par méthylation aberrante de l'ADN. Dans la lignée cellulaire métastatique colique, SW620, la réexpression de la protéine SOCS-1 provoque une inhibition des caractères invasifs. Cette transformation du phénotype cellulaire s'accompagne d'une réexpression de la E-cadherine à la membrane.