L'intégration 3DVLSI, également connue sous le nom d'intégration monolithique ou séquentielle, est présentée et évaluée dans cette thèse comme une alternative à la réduction du nœud technologique des circuits logiques CMOS. L’avantage principal de cette technologie par rapport à l'intégration parallèle 3D, déjà existante, est l'alignement précis entre les niveaux, ce qui permet des contacts 3D réduits et plus proches. Un autre avantage, extrêmement favorable à l’approche 3DVLSI, est l’amélioration du placement et du routage par rapport aux circuits planaires, notamment parce qu’elle permet des interconnexions plus courtes et qu’elle offre a un degré de liberté supplémentaire dans la direction Z pour la conception. Par exemple, les fils les plus longs dans les circuits planaires peuvent ainsi être réduits grâce aux contacts 3DCO, en diminuant les éléments parasites d'interconnexion. Il est ainsi possible d’augmenter la vitesse du circuit et de réduire la puissance électrique. Dans ce contexte, la thèse a été divisée en deux parties. La première partie traite de l’évaluation de la Consommation, des Performances et de la Surface (CPS) et donne des recommandations pour la conception des circuits 3D. La deuxième partie traite la variabilité des circuits 3D en utilisant un modèle statistique unifié, et en proposant une approche pour la variabilité des circuits multi-niveaux. / 3DVLSI integration, also known as monolithic or sequential integration is presented and evaluated in this thesis as a potential contender to continue the scaling for CMOS logic circuits. The main advantage of this technology compared to the already existing 3D parallel integration is its high alignment among tiers, enabling small size and pitch with the inter-tier contacts (3DCO). Another great 3DVLSI feature is its improved capability to place and route circuits, compared to the planar approach: the interconnections can be shorter as the design has an additional degree of freedom in the Z direction. For instance, long wires in planar circuits can cut thanks to 3DCO contacts, lowering the interconnection parasitic elements and speeding up the circuit as well as reducing the power. In this framework, the thesis has been divided into two parts: the first part is dedicated to the evaluation of Performance, Power and Area (PPA) of 3D circuits and gives design guidelines. The second part treats the variability in 3D circuits by using a 3D unified statistical model and propose an approach for the multi-tier variability.

La prolifération des composants électroniques fait que l'étude de leur vulnérabilité face à des agressions électromagnétiques intentionnelles ou non devient de plus en plus préoccupante. Notre étude s'inscrit dans ce contexte et s'oriente plus particulièrement vers les composants numériques. Ces derniers incorporent généralement, à toutes leurs interfaces d'entrée et de sortie, des éléments de protection contre les décharges électrostatiques permettant d'éliminer tout signal se présentant avec une amplitude élevée. Cependant, les signaux perturbateurs peuvent avoir des amplitudes moindres mais des formes d'onde complexes et capables de causer des dysfonctionnements à ces composants numériques sans activer les protections. Dans ce cas, les étages d'entrée se retrouvent au premier plan et leur comportement face à ces signaux perturbateurs peut altérer la fonctionnalité globale du circuit. Ainsi, nous nous sommes proposés d'étudier et de modéliser les comportements de ces étages d'entrée face à ces types d'agressions. Une première étape a consisté à définir une plateforme d'expérimentation pour les composants numériques. Une sélection des types de composants de test a d'abord été effectuée et le choix s'est porté naturellement sur l'inverseur CMOS, car il est présent sur la quasi-totalité des étages d'entrée, et sa structure est simple et connue. Le choix de cette technologie est également dicté par sa simplicité et son omniprésence dans les équipements électroniques actuels. Différents types de signaux perturbateurs ont été appliqués à ces inverseurs CMOS afin d'observer et de relever leurs comportements typiques et particuliers. Ensuite, à partir des résultats expérimentaux, un modèle SPICE comportemental et générique des inverseurs CMOS a été créé. Différents types de modèles de composants numériques existent mais le type SPICE est le seul à expliciter leur architecture complète. En effet, pour des raisons liées aux propriétés intellectuelles, les fabricants sont généralement discrets sur les structures internes de leurs circuits intégrés. Par contre, ces modèles SPICE ne sont à priori valables que dans des limites de fonctionnement définis par les fabricants. Nous avons apporté diverses modifications à ce modèle afin d'incorporer les comportements observés en dehors des limites de fonctionnement des inverseurs CMOS. Le besoin de trouver un modèle générique a imposé d'étudier un grand nombre d'échantillons d'inverseurs CMOS de différents fabricants et de différentes familles technologies. Enfin, une synthèse des résultats de simulations et des modèles, en fonction des fabricants et des familles technologiques, a été réalisée sous forme d'un tableau récapitulatif. / The proliferation of electronic components increases the interest of investigations about their vulnerability against electromagnetic interference intentionally emitted or not. Our study falls in this context and is specifically devoted to digital devices. These devices usually include, at their input/output ports, protection elements to prevent against electrostatic discharges and all kind of signals with very high amplitude. However, the perturbating signals can have low amplitude and complex waveforms that can cause trouble to these digital devices without triggering protection elements. In this case, first stages are the front, and their behaviors against these perturbation signals can alter the good operation of the device. Thus, we propose to study and model the behaviors of these first stages against such aggressions. First of all, an experimental platform was defined for the digital devices. A selection of devices is done and CMOS inverter was naturally chosen because of its presence in almost all of the first stages of digital devices, and because its structure is simple and well known. The choice of the CMOS technology is also due to its simplicity and omnipresence in current electronic equipments. Different perturbation signals were applied to these CMOS inverters to observe and record their typical and particular behaviors. Secondly, with the experimental results, a behavioral and generic SPICE model of CMOS inverters was developed. Different models exist for digital devices, but SPICE is the only one explicitly describing their complete architecture. But, for intellectual proprieties reasons, the manufacturers are usually reluctant to share information on their devices’ internals. However, the SPICE models are only valid within some operating limits defined by manufacturers. We have brought different modifications to this SPICE model to incorporate the observed behaviors of CMOS inverters inside and outside their normal operating conditions. The generic criterion of the final model imposed to study a large number of CMOS inverters of different manufacturers and different logic families. Finally, a synthesis of models and simulation results, by manufacturer and logic family, is produced.

Elektronik för extrema miljöer, som kan användas vid hög temperatur, hög strålning och omgivning med frätande gaser, har varit starkt önskvärd vid utforskning av rymden och övervakning av kärnreaktorer. Kiselkarbid (SiC) är en av kandidaterna inom material för extrema miljöer på grund av sin höga temperatur- och höga strålnings-tolerans. Syftet med denna avhandling är att karakterisera 4H-SiC MOSFETar vid hög temperatur och att konstruera SPICE modeller för 4H-SiC MOSFETar. MOSFET-transistorer karakteriserades till 500°C. Med användande av karaktäristik för en 4H-SiC NMOSFET med L/W = 10 µm / 50 µm, anpassades en SPICE LEVEL 2 kretsmodell. Modellen beskriver DC karakteristiska av 4H- SiC MOSFETar mellan 25ºC och 450ºC. Baserat på SPICE-kretsmodellen simulerades egenskaper för operationsförstärkare och digitala inverterar. Därutöver analyserades driften av pseudo-CMOS vid hög temperatur och principen för konstruktion av pseudo-CMOS föreslogs. Arean och utbytet (s.k. yield) av pseudo-CMOS integrerade kretsar uppskattades och det visar sig att SiC pseudo-CMOS integrerade kretsar kan använda mindre area än SiC CMOS integrerade kretsar. / Harsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance.‌ The objective of this thesis is to characterize 4H-SiC MOSFETs at high- temperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of 25 – 450ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-CMOS at high-temperature was analyzed and the operation principle of pseudo-CMOS was suggested. The device area and yield of pseudo-CMOS integrated circuits were estimated and it is shown that SiC pseudo-CMOS integrated circuits can use less area than SiC CMOS integrated circuits.

CP47,497 and other synthetic cannabinoid compounds were incipiently synthesized as research tools to investigate the mechanisms by which marijuana affects the brain and to aid in the development of therapeutic agents. Recently, these cannabinoid compounds have resurfaced in the designer drug market, marketed as “herbal incense products” (HIPs). Their popular use has resulted in an alarming rate of reported adverse effects and toxicities. Current legislation classified CP47,497 and several other synthetic cannabinoids compounds as Schedule I agents, but abuse of these compounds persists with serious consequences to public health and safety. In vivo studies examining the behavioral consequences of abused synthetic cannabinoids are limited. As a result, the goals of this research were to elucidate the acute and chronic pharmacological effects of CP47,497 and to develop a bioanalytical method for CP47,497 drug detection in mice. Cannabimimetic effects were evaluated in well-established in vivo models, the tetrad paradigm and drug discrimination assay. The tetrad test is comprised of four outcome measures sensitive to the primary psychoactive cannabinoid present in marijuana, delta-9-tetrahydrocannabinol (THC): catalepsy (bar test), antinociception (tail withdrawal latency), hypothermia, and decreases in spontaneous locomotor activity. While many pharmacological agents can produce one or a subset of these tetrad effects, drugs that activate CB1 receptors produce characteristic effects in all four parameters. An HPLC/MS/MS method was developed and confirmed the presence of CP47,497 in brain. We investigated whether CB1 receptors mediate the pharmacological effects of CP47,497. Cumulative dose-response experiments determined CP47,497 is more potent than THC in vivo in using multiple behavioral assays. Complementary pharmacological (CB1 receptor antagonist, rimonabant) and genetic (CB1 (-/-) mice) approaches were used to investigate whether CB1 receptors mediate the effects of CP47,497. Rimonabant (3 mg/kg or 10 mg/kg, depending on independent measure) blocked all cannabinoid-like pharmacological effects of CP47,497. Supporting these findings, CB1(-/-) mice were resistant to cannabimimetic effects of CP47,497. CP47,497 fully substituted for THC in the drug discrimination assay, with a potency of more than 5 times that of THC. Collectively, these results indicate that CP47,497 is markedly more potent (i.e. 5-8 fold) than THC, and its repeated administration produces tolerance to the cataleptic, antinociceptive, hypothermic and hypolocomotor effects in mice, with significant presentation of somatic withdrawal signs (paw flutter and head shakes) upon drug cessation. These findings are consistent with the high incidence of adverse events in humans abusing synthetic cannabinoids.

Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed<br>successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size<br>and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the<br>Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed<br>signals based systems.<br>Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices<br><div>for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.</div><div>GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design<br>Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power<br>amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as<br>low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. <br></div><div>These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic<br>Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and<br>digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.<br></div><div><br></div>

Fluxo de síntese física baseado em standard cells tem sido utilizado na indústria e academia já há um longo período de tempo. Esta técnica é conhecida por ser bastante confiável e previsível uma vez que a mesma biblioteca de células, que foi devidamente validada e caracterizada, pode ser utilizada em diferentes projetos. No entanto, há uma série de otimizações lógicas e elétricas para problemas como: redução do consumo estático, circuitos assíncronos, SEU, NBTI, DFM, etc. que demandam a existência de células inexistentes em bibliotecas tradicionais. O projeto do leiaute destas células é usualmente feito a mão, o que pode dificultar a adoção e desenvolvimento de novas técnicas. Neste trabalho foi desenvolvido uma ferramenta para síntese automática do leiaute de redes de transistores chamada ASTRAN. Esta ferramenta suporta geração de células irrestrita quanto ao tipo da rede de transistores, incluindo lógica não-complementar, auxiliando no desenvolvimento de circuitos otimizados com menor área, número de transistores, conexões, contatos e vias. Através da utilização de uma nova metodologia para compactação do leiaute com programação linear mista com inteiros (MILP), foi possível compactar eficientemente as geometrias das células simultaneamente em duas dimensões, além de lidar com regras de projeto condicionais existentes em tecnologias abaixo de 130nm. ASTRAN conseguiu obter ganhos de produtividade uma ordem de grandeza superior ao do projeto exclusivamente manual, necessitando de apenas 12h para gerar células com até 44 transistores. Na comparação com standard cells comerciais - considerado o pior caso uma vez que o ganho estaria justamente em gerar células inexistentes nestas bibliotecas ou então utilizar a ferramenta para obter um leiaute inicial antes de otimizá-lo a mão - o resultado foi bastante próximo, sendo que 71% das células geradas com o ASTRAN apresentaram exatamente a mesma área. / Cell library-based synthesis flows for ASICs is one of the most used methodologies in both industry and academia for design of VLSI. It is known to be very reliable and predictable since the same cell library can be characterised and used in several different designs. However, there is a number of logic and electric optimizations for problems like: leakage reduction, asynchronous circuits, SEU, NBTI, DFM, etc. that demands the development of new cells. These cell layouts are usually designed by hand, which can limit the adoption and development of promising techniques. This work presents the development of a tool for automatic synthesis of transistor networks called ASTRAN. It can generate cell layout with unrestricted cell structure, including non-complementary logic cells, supporting the developing of optimized circuits with smaller number of transistors, connections, contacts and vias. By using a new methodology for simultaneous two-dimensional (2D) layout compaction using mixed integer linear programming (MILP), we were able to support most of the conditional design rules that applies to technology nodes bellow 130nm, while producing as result dense cell layouts. We demonstrate that ASTRAN can generate layouts with a very smal area overhead compared to commercial standard-cells and can improve productivity in one order of magnitude when compared to the manual design of the cells. Gates containing up to 44 transistors were generated in less than 12h of run-time.

Ce travail de thèse traite de la conception, de l'optimisation et de la modélisation électrique d'une nouvelle génération de composants MOS de puissance, appelés FLIMOS (FLoating Islands MOSFET). La structure FLIMOS permet une nette amélioration de la résistance à l'état passant des transistors MOS de puissance. Comparée à la structure à Superjonction, la structure FLIMOS est très intéressante pour les faibles et moyennes tensions de claquage. Dans un premier temps, nous avons proposé une approche analytique permettant d'estimer la tension de claquage, la résistance passante spécifique et les capacités inter-électrodes de la structure FLIMOS. Par conséquent, nous avons défini la plage des dopages "utiles" de la zone de drift pour laquelle la structure FLIMOS était optimisée. Ensuite, nous avons démontré que le concept des îlots flottants ne dégradait pas les performances dynamiques des composants MOS de puissance. Dans un deuxième temps, un nouveau modèle SPICE des transistors MOS de puissance basse tension à canal court, a été proposé pour la première fois. Ce modèle décrit d'une façon plus exacte la zone de transition entre la zone linéaire et la zone de saturation du transistor MOS de puissance et tient compte, en plus, des effets du canal court sur la tension de seuil et la mobilité. Les paramètres de ce nouveau modèle sont les mêmes que ceux du modèle SPICE niveau 3. Enfin, le modèle a été validé en comparant les résultats des simulations SPICE aux valeurs mesurées.

Cette thèse a pour thème la contribution à lélaboration de méthodologies et doutils daide à la conception de systèmes multi-technologiques. Ces travaux de recherche et de développement s'inscrivent dans le cadre dun projet européen portant sur la simulation basée sur les spécifications et les indicateurs de performance au regard des effets thermiques et électriques. L'objectif est de créer une plate-forme de modélisation permettant de voir les modèles certifiés et de répondre aux critères fixés en se concentrant sur la fonction, le comportement et la structure, et la physique du composant. Cette plate-forme met en oeuvre des procédures (langage VHDL-AMS, méthodologies, ) et des ressources (outils de CAO, bibliothèques, ). Une telle plate-forme repose sur des bases conceptuelles alliant méthodes de conception (approches descendante et ascendante) et méthodes de modélisation (fonctionnelle, comportementale et structurelle, physique).

With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.

Lietuvoje prieskoninės arbatos tampa populiaresnės, dėl prieskonių ir žolių vis labiau atskleidžiamų teigiamų savybių žmogaus sveikatai. Tačiau jų pasirinkimas yra dar nedidelis. Tyrimo tikslas buvo sukurti kelias prieskoninių arbatų kompozicijas ir įvertinti jų juslines savybes bei antimikrobinį poveikį. Buvo sukurtos keturios arbatų kompozicijos: „Virškinimo arbata“, „Rytinė arbata“, „Vakarinė arbata“ ir „Afrodiziakas“. Arbatų kompozicijos buvo maišomos namų sąlygomis. Juslinės savybės vertintos taikant juslinės aprašomosios analizės metodus. Specialiai apmokyta 6 vertintojų grupė atrinko pagrindines arbatų kompozicijų savybes. Antimikrobinės arbatų kompozicijų savybės buvo įvertintos difuzijos į agarą metodu prieš Staphylococcus epidermidis, Staphylococcus aureus, Escherichia coli, Salmonella typhimurium. Atlikta arbatų kompozicijų juslinė analizė parodė, kad skirtingos sudėties arbatos mėginiai skyrėsi instrumentiniu metodu įvertintos spalvos charakteristikomis. Juslinės skonio ir kvapo savybės priklausė nuo arbatos sudėties, ir nors visų arbatos mėginių skonis ir kvapas buvo gana intensyvūs, sodrūs, tačiau atskiri jaučiami skoniai ir kvapai priklausė nuo arbatos sudėties. Preliminarus priimtinumo vertinimas parodė, kad „Afrodiziako“ arbatos skonis ir kvapas vertintas kaip mažiau priimtini nei kitų arbatos mėginių, gal būt, todėl, kad jos skonis, kvapas bei pojūtis burnoje labiau priminė buljoną nei arbatą, o tai daugeliui vartotojų yra neįprasta. Priimtino vartotojams... [toliau žr. visą tekstą] / Spice tea is becoming more popular in Lithuania regarding spices and herbs growing disclosed positive characteristics to human health. However, their selection is still limited. The goal of the research was to create a few teas compositions of spices and evaluate the organoleptic characteristics and antimicrobial effect. There were created four tea compositions, "Digestive Tea", "Morning Tea", "Evening Tea" and "Aphrodisiac". Tea compositions were home-made. Organoleptic characteristics were tested using descriptive sensory analysis methods. Specially trained 6 assessors group has sorted main characteristics of the tea compositions. Antimicrobial compositions of tea were evaluated by the agar diffusion method against Staphylococcus epidermidis, Staphylococcus aureus, Escherichia coli, Salmonella typhimurium. Analysed teas sensory compositions showed that differences were found in tea compositions characteristics based on instrumental colour analysis instrumental method. Sensory flavour and aroma characteristics were based on the tea composition, despite all tea samples – flavour and fragrance were quite intense, however separately felt flavours and fragrances were based on, composition of tea. Preliminary assessment of the acceptability showed that the "Aphrodisiac" tea flavour and aroma selected as less acceptable than other tea samples, perhaps because of its taste, aroma and mouth feel were more like as broth than tea, which is unusual for most of the users. To consumers... [to full text]